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PLL130-68 Datasheet

Manufacturer: PhaseLink Corporation
PLL130-68 datasheet preview

Datasheet Details

Part number PLL130-68
Datasheet PLL130-68_PhaseLinkCorporation.pdf
File Size 257.51 KB
Manufacturer PhaseLink Corporation
Description High Speed Translator Buffers
PLL130-68 page 2 PLL130-68 page 3

PLL130-68 Overview

The PLL130-68 and PLL130-69 are low cost, high performance, high speed, translator buffers that reproduce any input frequency from DC to 1.0GHz. They provide a pair of differential outputs (PECL for PLL130-68 or LVDS for PLL13069). Thanks to an internal AC coupling of the reference input (REFIN), any input signal with at least 100mV swing can be used as reference signal, regardless of its DC value.

PLL130-68 Key Features

  • Accepts any single-ended REFIN input (with as low as 100mV swing)
  • Internal AC coupling of REFIN
  • Input range from 1.0MHz to 1.0 GHz
  • No Vref required
  • No external current source required
  • 2.5 to 3.3V operation
  • Available in 3x3mm QFN
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More Datasheets from PhaseLink Corporation

See all PhaseLink Corporation datasheets

Part Number Description
PLL130-69 High Speed Translator Buffers
PLL130-05 High Speed Translator Buffer to PECL
PLL130-07 High Speed Translator Buffer to CMOS
PLL130-08 High Speed Translator Buffer to PECL
PLL130-09 High Speed Translator Buffer to LVDS
PLL102-03 Low Skew Output Buffer
PLL102-04 Low Skew Output Buffer
PLL102-05 Low Skew Output Buffer
PLL102-10 Low Skew Output Buffer
PLL102-108 Programmable DDR Zero Delay Clock Driver

PLL130-68 Distributor

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