PL613-21 Datasheet | PhaseLink Corporation

FEATURES - Designed for PCB Space Savings with 3 Low Power Programmable PLLs - Ultra Low-Power Consumption - Ultra-Low Power Down Mode, <5A Typical - CLK1 Capable of Generating 32.768k Hz - Individual Output Buffer VDD Pins for Flexible Output Voltages, 1.8V to 3.3V, ±10% - Individual PLL Power Down Control - Output Frequency (based on VDD_CORE voltage): o <65MHz @ 1.8V operation o <90MHz @ 2.5V operation o <125MHz @ 3.3V operation - Input Frequency: o Fundamental Crystal: 10MHz to 40MHz o Reference Input: 10MHz to 200MHz - Active Low or Hi-Z Disabled Output State - 1.8V to 3.3V, ±10% Core Power Supply - 1.8V to 3.3V, ±10% Buffer Power Supply - Operating Temperature Ranges: o mercial: 0C to 70C o Industrial: -40C to 85C - Available in GREEN/Ro HS pliant 3x3 QFN Package PIN CONFIGURATION GND XIN/FIN XOUT VDD_CORE PDB4 CLK4 VDD4 PDB1 12 11 10 9 13 8 14 P61321 7 XXX(I) 15 6 16 5 1 23 4 CLK3 PDB2_3 VDD2_3 CLK2 CLK1 VDD1 GND GND QFN-16L Package DESCRIPTION The PL613-21 is an...