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PhaseLink Corporation

PL613-05 Datasheet Preview

PL613-05 Datasheet

3 Output Clock IC

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(Preliminary)PL613-05
1.8V-3.3V PicoPLL, 3-PLL, 200MHz, 3 Output Clock IC
FEATURES
DESCRIPTION
Designed for PCB space savings with 3 low-power The PL613-05 is an advanced triple PLL design
Programmable PLLs and 3 distinct clock outputs.
based on PhaseLink’s PicoPLL, world’s smallest
Low-power consumption (<10µA when PDB is
activated)
programmable clock, technology. This flexible
programmable architecture is ideal for high
Output frequency:
performance, low-power, low-cost applications. When
o <110MHz @ 1.8V operation
using the power down (PDB) feature the PL613-05
o <166MHz @ 2.5V operation
consumes less than 10 µA of power. Besides its small
o <200MHz @ 3.3V operation
form factor and 3 distinct outputs that can reduce
Input frequency:
o Fundamental Crystal: 10MHz to 40MHz
o Reference Input: 10MHz to 200MHz
overall system costs, the PL613-05 offers superior
phase noise, jitter and power consumption
performance.
Programmable I/O pins can be configured as
Output Enable (OE), Power Down (PDB) inputs, or
Clock output.
Disabled outputs programmable as HiZ or
Active Low
Single 1.8V to 3.3V, ±10% power supply
Operating temperature range from -40°C to 85°C
Available in GREEN/RoHS compliant SOP-8L package.
PIN CONFIGURATION
XIN, FIN
CLK2, OEM^, PDB^
VDD
CLK0
1
2
3
4
8 XOUT
7 VDD
6 CLK1
5 GND
SOP-8L
^ Denotes internal pull up
BLOCK DIAGRAM
FREF
XIN/FIN
XOUT
Xtal FREF Programmable VCO1
OSC
PLL1
Odd/Even
Divider
(5-bits)
OEM
PDB
Programmable Function
Programmable VCO2
PLL2
FREF
Programmable VCO3
PLL3
Odd/Even
Divider
(5-bits)
Odd/Even
Divider
(5-bits)
%1, %2,
%4, %8
%1, %2,
%4, %8
CLK1
CLK0
CLK2, OEM, PDB
2880 Zanker Road, San Jose, CA 95134, (Tel) 408-571-1668, (Fax) 408-571-1688 www.phaselink.com Rev 09/16/11 Page 1




PhaseLink Corporation

PL613-05 Datasheet Preview

PL613-05 Datasheet

3 Output Clock IC

No Preview Available !

(Preliminary)PL613-05
1.8V-3.3V PicoPLL, 3-PLL, 200MHz, 3 Output Clock IC
PACKAGE PIN ASSIGNMENT
Name
Package
Pin #
Type
Description
XIN, FIN
CLK2, OEM, PDB
VDD
CLK0
GND
CLK1
XOUT
1
2
3, 7
4
5
6
8
I Crystal or Reference Clock input
- Programmable Clock (CLK2) output, or
B* - Output Enable Master (OEM) for all clock outputs, or
- Power Down mode (PDB) input
P VDD connection
B* Programmable Clock (CLK0) output
P GND connection
O Programmable Clock (CLK1) output
O Crystal output pin. Do Not Connect when using FIN
* Note: All bidirectional buffers (I/Os) incorporate an internal 60KΩ pull up resistor except when PDB mode is used. In
configurations that use PDB, the PDB pin will have a 10MΩ pull up resistor.
KEY PROGRAMMING PARAMETERS
CLK[ 0:2 ]
Output Frequency
CLK[0]
FVCO2 / P
CLK[1,2]
FVCOx / (P*(1,2,4,8)) or
FREF / (P*(1,2,4,8))
Where FVCO = FREF * M / R
M = 11 bit
R = 8 bit
P = 5 bit (Odd/Even Divider)
Output Drive Strength
Each output has three
optional drive strengths to
choose from. They are:
Low: 4mA
Std: 8mA (default)
High:16mA
Programmable Input/Output
Most pins are multi-function I/Os and can be
configured as:
OEM – (Master OE controlling all
outputs)
PDB – (Power Down)
CLK[0:2] – (Output)
HiZ or Active Low disabled state
2880 Zanker Road, San Jose, CA 95134, (Tel) 408-571-1668, (Fax) 408-571-1688 www.phaselink.com Rev 09/16/11 Page 2


Part Number PL613-05
Description 3 Output Clock IC
Maker PhaseLink Corporation
PDF Download

PL613-05 Datasheet PDF






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