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PhaseLink Corporation

PL611S-28 Datasheet Preview

PL611S-28 Datasheet

PicoPLLTM Programmable Clock

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P(Preliminary) L611s-28
1.8V-3.3V PicoPLLTM, World’s Smallest Programmable Clock
FEATURES
Designed for Very Low-Power applications
Offered in Tiny GREEN/RoHS compliant packages
o 6-pin DFN (2.0mmx1.3mmx0.6mm)
o 6-pin SC70 (2.3mmx2.25mmx1.0mm)
o 6-pin SOT23 (3.0mmx3.0mmx1.35mm)
Input Frequency:
o Fundamental Crystal: 10MHz to 50MHz
o Reference Input: 1MHz to 200MHz
www.DataSheet4UA.ccocmepts >0.1V reference signal input voltage
Output Frequency:
o <65MHz @ 1.8V operation
o <90MHz @ 2.5V operation
o <125MHz @ 3.3V operation
Disabled outputs programmable as HiZ or Active Low.
Low current consumption:
o <1.2mA @ 27MHz
o < 5µA when PDB is activated
Single 1.8V, 2.5V, or 3.3V ± 10% power supply
Operating temperature range from -40°C to 85°C
DESCRIPTION
The PL611s-28 consumes very low-power while
producing high performance clock outputs of up to
55MHz. Designed for low-power applications with
very stringent space requirement, PL611s-28
consumes about 1.2mA, while producing 2 distinct
outputs of 27MHz and 13.5MHz. Designed to fit in a
small SOT, SC70, or SOT23 package for high
performance applications, the PL611s-28 offers
excellent phase noise and jitter performance. The
power down feature of PL611s-28, when activated,
allows the IC to consume less than 5µA of power,
while its programming flexibility allows generating
any output, using a low-cost crystal or reference
input. In addition, one programmable I/O pin can be
configured as Output Enable (OE), Frequency
switching (FSEL), Power Down (PDB) input, or CLK1
(FOUT, FREF, FREF/2) output.
PACKAGE PIN CONFIGURATION
XIN/FIN
OE, PDB, FSEL, CLK1
GND
1
2
3
6 XOUT
5 VDD
4 CLK0
DFN-6L
(2.0mmx1.3mmx0.6mm)
GND
OE, PDB,
FSEL, CLK1
1
2
6 CLK0
5 VDD
XIN/FIN 3 4 XOUT
SC70-6L
(2.3mmx2.25mmx1.0mm)
OE, PDB,
FSEL, CLK1
GND
XIN/FIN
1
2
3
6 CLK0
5 VDD
4 XOUT
SOT23-6L
(3.0mmx3.0mmx1.35mm)
BLOCK DIAGRAM
XIN/FIN
XOUT
XTAL Fref R-counter
OSC
(8-Bit)
Programmable
CLoad
M-counter
(11-Bit)
Phase
Detector
Fvco=Fref* (2 * M /R)
Charge
Pump
Loop
Filter
VCO
P-counter
Fout=Fvco / (2 *P) (5-Bit)
CLK0
Programmable Function
Programming
Logic
OE, FSEL,
PDB, CLK1
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 3/9/07 Page 1




PhaseLink Corporation

PL611S-28 Datasheet Preview

PL611S-28 Datasheet

PicoPLLTM Programmable Clock

No Preview Available !

P(Preliminary) L611s-28
1.8V-3.3V PicoPLLTM, World’s Smallest Programmable Clock
KEY PROGRAMMING PARAMETERS
CLK[0:1]
Output Frequency
Output Drive Strength
FOUT = FREF * M / (R * P)
Where M = 11 bit
R = 8 bit
P = 5 bit
www.DataSheCetL4KU0.co=mFOUT, FREF or FREF / (2*P)
CLK1 = FREF, FREF/2, CLK0 or CLK0/2
Three optional drive strengths to
choose from:
Low: 4mA
Std: 8mA (default)
High: 16mA
Programmable
Input/Output
One output pin can be configured
as:
OE - input
PDB - input
FSEL – input
HiZ or Active Low disabled state
PACKAGE PIN ASSIGNMENT
Name
OE, PDB,
FSEL, CLK1
Pin Assignment
SOT SC70 DFN
Pin # Pin# Pin#
122
Type
I/O
Description
This programmable I/O pin can be configured as an Output Enable
(OE) input, Power Down (PDB) input, On-the-Fly Frequency Switching
Selector (FSEL)input or CLK1 clock output. This pin has an internal
60KΩ pull up resistor (OE, PDB & FSEL Only).
The OE and PDB features can be programmed to allow the output to
float (Hi Z), or to operate in the ‘Active low’ mode.
State
OE
PDB FSEL
0 Disable CLK Power Down Mode Frequency ‘2’
1 (default) Normal mode Normal mode
Frequency ‘1’
GND
XIN, FIN
XOUT
VDD
CLK0
2 1 3 P GND connection
3 3 1 I Crystal or Reference input pin
Crystal Output pin
4 4 6O
Do Not Connect (DNC ) when FIN is present
5 5 5 P VDD connection
6 6 4 O Programmable Clock Output
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 3/9/07 Page 2


Part Number PL611S-28
Description PicoPLLTM Programmable Clock
Maker PhaseLink Corporation
Total Page 9 Pages
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