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PhaseLink Corporation

PL611S-27 Datasheet Preview

PL611S-27 Datasheet

PicoPLLTM Programmable Clock

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P(Preliminary) L611s-27
1.8V to 3.3V PicoPLLTM Programmable Clock
FEATURES
Advanced One Time Programmable (OTP) PLL design
Programmable PLL or direct oscillation operation
Very low Jitter and Phase Noise (30-70ps Pk-Pk typical)
Output Frequency up to
o 65MHz @ 1.8V operation
o 9/MHz @ 2.5V operation
o 125MHz @ 3.3V operation
Reference Input Frequency: 1MHz to 200MHz
www.DataSheet4UA.ccocmepts >0.1V reference signal input voltage
Low current consumption, <10µA when PDB is
activated
One programmable I/O pin can be configured as
Output Enable (OE), Frequency Switching
(FSEL), or Power Down (PDB) input.
Disabled outputs programmable as HiZ or Active Low.
Single 1.8V, 2.5V, or 3.3V ± 10% power supply
Operating temperature range from 0°C to 70°C
Available in 6-pin SOT23 & DFN GREEN/RoHS
Compliant packages
DESCRIPTION
The PL611s-27 is a general purpose frequency
synthesizer and a member of PhaseLink’s PicoPLL
product family. Designed to fit in a small 6-pin DFN,
or 6-pin SOT package for high performance
applications, the PL611s-27 offers very low phase
noise, jitter, and power consumption, while offering 2
clock outputs. The Frequency Switching (FSEL)
capability of PL611s-27 allows for programming two
sets of frequencies, while the power down feature of
PL611s-27, when activated, allows the IC to
consume less than 10µA of power. PL611s-27’s
programming flexibility allows generating any output
using a Reference input signal.
PACKAGE PIN CONFIGURATION
FIN 1
CLK1 2
GND 3
6 OE, PDB, FSEL
5 VDD
4 CLK0
CLK1
GND
FIN
1
2
3
6 CLK0
5 VDD
4 OE, PDB, FSEL
DFN-6L
(2.0mmx1.3mmx0.6mm)
SOT23-6L
(3.0mmx3.0mmx1.35mm)
BLOCK DIAGRAM
FIN
Fref R-counter
(8-Bit)
M-counter
(11-Bit)
Phase
Detector
Fvco=Fref* (2 * M /R)
Charge
Pump
Loop
Filter
VCO
P-counter
(5-Bit) Fout=FVCO/(2*P)
CLK1
CLK0
Programmable Function
Programming
Logic
OE, PDB,
FSEL
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/25/07 Page 1




PhaseLink Corporation

PL611S-27 Datasheet Preview

PL611S-27 Datasheet

PicoPLLTM Programmable Clock

No Preview Available !

P(Preliminary) L611s-27
1.8V to 3.3V PicoPLLTM Programmable Clock
KEY PROGRAMMING PARAMETERS
CLK
Output Frequency
Output Drive Strength
FOUT = FREF * M / (R * P)
Where M = 11 bit
R = 8 bit
P = 5 bit
www.DataSheCetL4KU0.co=mFOUT, FREF or FREF / (2*P)
CLK1 = FREF, FREF/2, CLK0 or CLK0/2
Three optional drive strengths to
choose from:
Low: 4mA
Std: 8mA (default)
High: 16mA
Programmable
Input/Output
One output pin can be configured
as:
OE - input
PDB - input
FSEL – input
HiZ or Active Low disabled state
PACKAGE PIN ASSIGNMENT
Name
CLK1
GND
FIN
Pin Assignment
DFN SOT
Pin# Pin #
21
32
13
Type
O
P
I
Description
Programmable Clock Output
GND connection
Reference input pin
This programmable I/O pin can be configured as an Output Enable (OE)
input, Power Down (PDB) input or Frequency Switching (FSEL) input. This
pin has an internal 60KΩ pull up resistor.
OE,
PDB,
6
4
The OE and PDB features can be programmed to allow the output to float
I (Hi Z), or to operate in the ‘Active low’ mode.
FSEL
State
OE
PDB
FSEL
0 Disable CLK Power Down Mode Frequency ‘2’
1 (default) Normal mode Normal mode
Frequency ‘1’
VDD 5 5 P VDD connection
CLK0
4
6
O Programmable Clock Output
OE AND PDB FUNCTION DESCRIPTION
OE PDB Osc. PLL
CLK0
CLK1
1 N/A On On
0 N/A On Off
N/A 1 On On
N/A 0 Off Off
On
HiZ or Active Low
On
HiZ or Active Low
On
On
On
HiZ or Active Low
Note: HiZ or Active Low states are programmable functions and will be set per request.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/25/07 Page 2


Part Number PL611S-27
Description PicoPLLTM Programmable Clock
Maker PhaseLink Corporation
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PL611S-27 Datasheet PDF






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