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PhaseLink Corporation

PL611S-26 Datasheet Preview

PL611S-26 Datasheet

PicoPLLTM Programmable Clock

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P(Preliminary) L611s-26
1.8V-3.3V PicoPLLTM Programmable Clock
FEATURES
Advanced One Time Programmable (OTP) PLL design
Programmable PLL or direct oscillation operation
Very low Jitter and Phase Noise (30-70ps Pk-Pk
typical)
Output Frequency up to
o 133MHz @ 1.8V operation
o 166MHz @ 2.5V operation
www.DataSheet4U.coom200MHz @ 3.3V operation
Reference Input Frequency: 1MHz to 200MHz
Accepts >0.1V reference signal input voltage
Low current consumption, <10µA when PDB is
activated
One programmable I/O pin can be configured as
Output Enable (OE),Power Down (PDB) input or an
additional clock output (CLK1).
Frequency Switching (FSEL) capability
Single 1.8V, 2.5V, or 3.3V ± 10% power supply
Operating temperature range from -40°C to 85°C
Available in 6-pin SOT23 and DFN GREEN/RoHS
compliant packaging
DESCRIPTION
The PL611s-26 is a general purpose frequency
synthesizer and a member of PhaseLink’s PicoPLLTM
product family. Designed to fit in a small 6-pin DFN
or 6-pin SOT package for high performance
applications, the PL611s-26 offers very low phase
noise, jitter, and power consumption, while offering
up to 2 clock outputs.. The Frequency Switching
(FSEL) capability of PL611s-26 allows for
programming two sets of frequencies, while the
power down feature of PL611s-26, when activated,
allows the IC to consume less than 10µA of power.
PL611s-26’s programming flexibility allows
generating any output using Reference input signal.
BLOCK DIAGRAM
FIN
FREF R-Counter
(8-bit)
Phase
M-Counter
Detector
(11-bit)
Charge
Pump
FVCO = FREF * (2 * M/R)
Programmable Function
P-Counter
FOUT = FVCO / (2 * P) (5-bit)
Programming
Logic
Loop
Filter
VCO
CLK0
FSEL
OE, PDB,
CLK1
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 1




PhaseLink Corporation

PL611S-26 Datasheet Preview

PL611S-26 Datasheet

PicoPLLTM Programmable Clock

No Preview Available !

P(Preliminary) L611s-26
1.8V-3.3V PicoPLLTM Programmable Clock
KEY PROGRAMMING PARAMETERS
CLK
Output Frequency
Output Drive Strength
FOUT = FREF * M / (R * P)
Where M = 11 bit
R = 8 bit
P = 5 bit
CLK0 = FOUT, FREF or FREF / (2*P)
www.DataSheCetL4KU1.co=mFREF, FREF/2, CLK0 or CLK0/2
Three optional drive strengths to
choose from:
Low: 4mA
Std: 8mA (default)
High: 16mA
Programmable
Input/Output
One output pin can be configured
as:
OE - input
PDB - input
CLK1 – output
PACKAGE PIN CONFIGURATION AND DESCRIPTION
FIN 1
OE,PDB,CLK1 2
GND 3
6 FSEL
5 VDD
4 CLK0
OE, PDB, CLK1
GND
FIN
1
2
3
6 CLK0
5 VDD
4 FSEL
DFN-6L
(2.0mmx1.3mmx0.6mm)
SOT23-6L
(3.0mmx3.0mmx1.35mm)
PIN DESCRIPTION
Name
OE,
PDB,
CLK1
Pin Assignment
DFN Pin# SOT Pin #
21
Type
I/O
Description
This programmable I/O pin can be configured as an Output Enable (OE)
input, Power Down input (PDB) or CLK1 Clock output. This pin has an
internal 60KΩ pull up resistor (OE and PDB functions only).
Pin State
OE
PDB
0
1 (default)
Disable CLK
Normal mode
Power Down Mode
Normal mode
GND 3
FIN 1
FSEL
6
VDD
CLK0
5
4
2 P GND connection
3 I Reference input pin
Frequency Switching Input pin. This pin has an internal 60KΩ pull up
resistor.
4I
FSEL
0
State
Frequency 2
1 (default)
Frequency 1
5 P VDD connection
6 O Programmable Clock Output
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 2


Part Number PL611S-26
Description PicoPLLTM Programmable Clock
Maker PhaseLink Corporation
Total Page 8 Pages
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