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PhaseLink Corporation

PL611S-17 Datasheet Preview

PL611S-17 Datasheet

PicoPLLTM KHz to MHz Programmable Clock

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P(Preliminary) L611s-17
1.8V-3.3V PicoPLLTM KHz to MHz Programmable Clock
FEATURES
Advanced Programmable PLL design for low-
frequency (kHz) input applications.
Input Frequency: 10kHz to 200MHz
OTP selectable AC/DC Input Coupling.
Accepts >0.1V reference signal input voltage
Very low Jitter and Phase Noise
Output Frequency:
www.DataSheet4U.coom <65MHz @ 1.8V operation
o <90MHz @ 2.5V operation
o <125MHz @ 3.3V operation
Disabled outputs programmable as HiZ or Active Low.
Offered in Tiny GREEN/RoHS compliant packages
o 6-pin DFN (2.0mmx1.3mmx0.6mm)
o 6-pin SC70 (2.3mmx2.25mmx1.0mm)
o 6-pin SOT23 (3.0mmx3.0mmx1.35mm)
Single 1.8V, 2.5V, or 3.3V ± 10% power supply
Operating temperature range from -40°C to 85°C
DESCRIPTION
The PL611s-17 is a low-cost general purpose
frequency synthesizer and a member of PhaseLink’s
PicoPLLTM Factory Programmable ‘Quick Turn Clock
(QTC)’ family. Designed to fit in a small SOT23,
SC70, or DFN package for high performance, low
power applications, the PL611s-17 accepts a low
frequency (>10KHz) Reference input and generates
up to 125MHz outputs with the best phase noise,
jitter performance, and power consumption for
handheld devices and notebook applications. In
addition, one programmable I/O pin can be
configured as Output Enable (OE), Frequency
switching (FSEL), Power Down (PDB) input, or CLK1
(FOUT, FREF, FREF/2) output. Cascading the PL611s-
17 with other PicoPLL ICs can result in producing all
required system clocks with specific savings in board
space, power consumption, and cost.
PACKAGE PIN CONFIGURATION
FIN
OE, PDB, FSEL, CLK1
VDD
1
2
3
6 LF
5 GND
4 CLK0
DFN-6L
(2.0mmx1.3mmx0.6mm)
OE, PDB,
FSEL, CLK1
1
6
CLK0
VDD 2 5 GND
FIN 3 4 LF
SC70-6L
(2.3mmx2.25mmx1.0mm)
LF
GND
CLK0
1
2
3
6 FIN
5
OE, PDB,
FSEL, CLK1
4 VDD
SOT23-6L
(3.0mmx3.0mmx1.35mm)
BLOCK DIAGRAM
FIN
Ref. R-Counter
(7-bit)
Phase
M-Counter
Detector
(16-bit)
FVCO = FRef * (M/R)
Charge
Pump
VCO
Programmable
Function
P-Counter
FOut = FVCO /2*P (4-bit)
Programming
Logic
CLK0
OE, PDB,
FSEL, CLK1
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/04/07 Page 1




PhaseLink Corporation

PL611S-17 Datasheet Preview

PL611S-17 Datasheet

PicoPLLTM KHz to MHz Programmable Clock

No Preview Available !

P(Preliminary) L611s-17
1.8V-3.3V PicoPLLTM KHz to MHz Programmable Clock
KEY PROGRAMMING PARAMETERS
CLK
Output Frequency
Output Drive Strength
FOUT = FREF * (M / R) /(2*P)
Where M=16 bit
R= 7 bit
P= 4 bit
CLK0 = FOUT, FREF or FREF / (2*P)
www.DataSheCetL4KU1.co=mFREF, FREF/2, CLK0 or CLK0/2
Three optional drive strengths to
choose from:
Low: 4mA
Std: 8mA (default)
High: 16mA
Programmable
Input/Output
One output pin can be configured as:
OE - input
FSEL - input
PDB - input
CLK1 – output
HiZ or Active Low disabled state
PACKAGE PIN ASSIGNMENT
Name
VDD
SOT
Pin#
1
Pin #
SC70
Pin#
2
DFN
Pin#
3
Type
P
Description
VDD connection.
This programmable I/O pin can be configured as Output Enable (OE)
input, Power Down (PDB) input, Frequency Selector (FSEL) or CLK1
clock output. This pin has an internal 10MΩ pull up resistor (OE, PDB &
FSEL Only).
OE, PDB,
FSEL, CLK1
2
1
The OE and PDB features can be programmed to allow the output
2 I/O to float (Hi Z), or to operate in the ‘Active low’ mode.
State
OE
PDB FSEL
0 Disable CLK Power Down Mode Frequency ‘2’
1 (default) Normal mode
Normal mode
Frequency ‘1’
FIN
LF
GND
CLK0
3 3 1 I Reference input pin.
4 4 6 I Loop Filter input pin.
5 5 5 P GND connection
6 6 4 O Programmable Clock Output
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/04/07 Page 2


Part Number PL611S-17
Description PicoPLLTM KHz to MHz Programmable Clock
Maker PhaseLink Corporation
Total Page 9 Pages
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