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PhaseLink Corporation

PL611S-06 Datasheet Preview

PL611S-06 Datasheet

Low-Power Programmable Quick Turn ClockTM

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P(Preliminary) L611s-06
Low-Power Programmable Quick Turn ClockTM
FEATURES
Advanced low-power, space saving programmable
PLL design
Very low Jitter and Phase Noise (30-70ps Pk-Pk typical)
Up to 2 programmable clock outputs
CMOS output frequency up to 35MHz.
Accepts Crystal or Ref Clock input
www.DataSheet4Uo.comFundamental Crystal: 10MHz to 30MHz
o Reference Input: 1MHz to 100MHz
Accepts >0.1V reference signal input voltage
Single 1.8V, 2.5V, or 3.3V ± 10% power supply
Operating temperature range from -40°C to 85°C
Available in 6-pin DFN, SC70, and SOT23, GREEN /RoHS
compliant packages
DESCRIPTION
The PL611s-06 is a low-power general purpose
frequency synthesizer and a member of PhaseLink’s
Programmable ‘Quick Turn Clock (QTC)’ family.
PhaseLink’s PL611s-06 can generate two system
clock frequencies of up to 35MHz from a 10MHz to
30MHz fundamental crystal or a 1MHz to 100MHz
Reference clock source. The PL611s-06 offers the
best phase noise and jitter performance, and power
consumption of its rivals. Cascading of the ICs to
produce additional clock frequencies is also
supported.
PACKAGE PIN CONFIGURATION
XIN, FIN 1
OE, CLK1 2
GND 3
GND 1 6 CLK0
6
5
XOUT
VDD
OE, CLK1
2
5 VDD
4 CLK0 XIN, FIN 3 4 XOUT
DFN-6L
(2.0mmx1.3mmx0.6mm)
SC70-6L
(2.3mmx2.25mmx1.0mm)
OE, CLK1 1 6 CLK0
GND 2 5 VDD
XIN, FIN 3 4 XOUT
SOT23-6L
(3.0mmx3.0mmx1.35mm)
BLOCK DIAGRAM
XIN/FIN
XOUT
XTAL
OSC
Programmable
CLoad
FREF
R-Counter
(8-bit)
M-Counter
(11-bit)
Phase
Detector
FVCO = FREF * (2 * M/R)
Charge
Pump
Loop
Filter
VCO
Programmable Function
P-Counter
FOUT = FVCO / ( 2 * P) (5-bit)
Programming
Logic
CLK
OE, CLK1
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 1




PhaseLink Corporation

PL611S-06 Datasheet Preview

PL611S-06 Datasheet

Low-Power Programmable Quick Turn ClockTM

No Preview Available !

P(Preliminary) L611s-06
Low-Power Programmable Quick Turn ClockTM
KEY PROGRAMMING PARAMETERS
CLK
Output Frequency
Output Drive Strength
FOUT = FREF * M / (R * P)
Where M = 11 bit
R = 8 bit
P = 5 bit
CLK0 = FOUT, FREF or FREF / (2*P)
www.DataSheCetL4KU1.co=mFREF, FREF/2, CLK0 or CLK0/2
Three optional drive strengths to
choose from:
Low: 4mA
Std: 8mA (default)
High: 16mA
Programmable
Input/Output
One output pin can be configured
as:
OE - input
CLK1 – output
PACKAGE PIN ASSIGNMENT
Name
Pin Assignment
SOT23
SC70
DFN
Pin #
Pin# Pin#
OE, CLK1
1
22
GND
XIN, FIN
XOUT
VDD
CLK0
2
3
4
5
6
13
31
46
55
64
Type
Description
This programmable I/O pin can be configured as an
B
Output Enable (OE) input, or CLK1 output. This pin
has an internal 60KΩ pull up resistor (OE Function
Only).
P GND connection
I Crystal or Reference input pin
Crystal Output pin
O
Do Not Connect (DNC ) when FIN is present
P VDD connection
O Programmable Clock Output
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 2


Part Number PL611S-06
Description Low-Power Programmable Quick Turn ClockTM
Maker PhaseLink Corporation
PDF Download

PL611S-06 Datasheet PDF






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