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PhaseLink Corporation

PL611S-02 Datasheet Preview

PL611S-02 Datasheet

Smallest Programmable Clock

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P(Preliminary) L611s-02
1.8V-3.3V PicoPLLTM, World’s Smallest Programmable Clock
FEATURES
Lowest-power, smallest Programmable PLL
Very low Jitter and Phase Noise
Output Frequency up to:
o 133MHz @ 1.8V operation
o 166MHz @ 2.5V operation
o 200MHz @ 3.3V operation
Input Frequency:
o Fundamental Crystal: 10MHz to 50MHz
www.DataSheet4U.coomReference Clock: 1MHz to 200MHz
Accepts >0.1V reference signal input voltage
One I/O pin can be configured as Output Enable (OE),
Frequency switching (FSEL), Power Down (PDB)
input, or CLK1 output.
<10µA current consumption with PDB active.
Single 1.8V, 2.5V, or 3.3V ± 10% power supply
Operating temperature range from -40°C to 85°C
Available in 6-pin DFN, SOT23, and SC70
GREEN/RoHS compliant packages.
DESCRIPTION
The PL611s-02 is a low-power, small form factor,
high performance OTP-base programmable
frequency synthesizer and a member of PhaseLink’s
PicoPLL Factory Programmable ‘Quick Turn Clocks.
Designed to fit in a small DFN, SC70, or SOT23
package for a broad range of applications, the
PL611s-02 offers the best phase noise and jitter
performance, and power consumption of its rivals. .
In addition, one programmable I/O pin can be
configured as Output Enable (OE), Frequency
switching (FSEL), Power Down (PDB) input, or CLK1
(FOUT, FREF, FREF/2) output. The power down
feature of PL611s-02, when activated, allows the IC
to consume less than 10µA of power, while its
programming flexibility allows generating any output,
up to 200MHz using a low-cost crystal or reference
input.
PACKAGE PIN CONFIGURATION
XIN/FIN 1
OE, PDB, FSEL, CLK1 2
GND 3
6 XOUT
5 VDD
4 CLK0
GND
OE, PDB,
FSEL, CLK1
XIN/FIN
1
2
3
6 CLK0
5 VDD
4 XOUT
DFN-6L
(2.0mmx1.3mmx0.6mm)
BLOCK DIAGRAM
SC70-6L
(2.3mmx2.25mmx1.0mm)
OE, PDB,
FSEL, CLK1
GND
XIN/FIN
1
2
3
6 CLK0
5 VDD
4 XOUT
SOT23-6L
(3.0mmx3.0mmx1.35mm)
XIN/FIN
XOUT
XTAL
OSC
Programmable
CLoad
FREF
R-Counter
(8-bit)
M-Counter
(11-bit)
Phase
Detector
FVCO = FREF * (2 * M/R)
Charge
Pump
Loop
Filter
VCO
Programmable Function
P-Counter
FOUT = FVCO / ( 2 * P) (5-bit)
Programming
Logic
CLK0
OE, PDB,
FSEL, CLK1
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 1




PhaseLink Corporation

PL611S-02 Datasheet Preview

PL611S-02 Datasheet

Smallest Programmable Clock

No Preview Available !

P(Preliminary) L611s-02
1.8V-3.3V PicoPLLTM, World’s Smallest Programmable Clock
KEY PROGRAMMING PARAMETERS
CLK
Output Frequency
Output Drive Strength
FOUT = FREF * M / (R * P)
Where M = 11 bit
R = 8 bit
P = 5 bit
CLK0 = FOUT, FREF or FREF / (2*P)
www.DataSheCetL4KU1.co=mFREF, FREF/2, CLK0 or CLK0/2
Three optional drive strengths to
choose from:
Low: 4mA
Std: 8mA (default)
High: 16mA
Programmable
Input/Output
One output pin can be configured
as:
OE - input
PDB - input
FSEL - input
CLK1 – output
PACKAGE PIN ASSIGNMENT
Name
Pin Assignment
SOT23 SC70 DFN
Pin # Pin# Pin#
Type
Description
This programmable I/O pin can be configured as an Output
Enable (OE) input, Power Down input (PDB), On-the-Fly
Frequency Switching Selector (FSEL), or CLK1 clock output
This pin has an internal 60KΩ pull up resistor for OE, PDB &
OE, PDB,
FSEL, CLK1
1
2
2 I/O FSEL.
State
OE
PDB FSEL
0 Tri-State CLK Power Down Mode Frequency ‘2’
1 (default) Normal mode Normal mode Frequency ‘1’
GND
XIN, FIN
XOUT
VDD
CLK0
2 1 3 P GND connection
3 3 1 I Crystal or Reference Clock input pin
Crystal Output pin
4 46O
Do Not Connect (DNC ) when FIN is present
5 5 5 P VDD connection
6 6 4 O Programmable Clock Output
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 2


Part Number PL611S-02
Description Smallest Programmable Clock
Maker PhaseLink Corporation
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PL611S-02 Datasheet PDF






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