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PhaseLink Corporation

PL611-30 Datasheet Preview

PL611-30 Datasheet

Programmable Quick Turn Clock

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PPreliminary L611-30
Programmable Quick Turn ClockTM
FEATURES
Advanced programmable PLL design
Very low Jitter and Phase Noise (< 40ps Pk-Pk typical)
Output frequency up to 375MHz CMOS.
Supports differential CMOS output to produce PECL,
LVDS inputs.
Crystal inputs:
o Fundamental crystal: 10MHz-30MHz
www.DataSheet4Uoo.comR3ReDfeorveenrctoenienpcurty:sUtapl:
Up to
to 200
75MHz
MHz
Accepts <1.0V reference signal input voltage
One programmable I/O pin can be configured as
Output Enable (OE), or Frequency Selection input
(FSEL), or Reference clock.
Single 3.3V ± 10% power supply
Operating temperature range from -40°C to 85°C
Available in 8-pin MSOP/SOIC, 6-pin SOT Green/
RoHS compliant packages.
PIN CONFIGURATION
XIN/FIN
GND
CLK0
CLK1
18
27
36
45
SOP-8
MSOP-8
XOUT
CLK2, OE, FSEL
DNC
VDD
DESCRIPTION
The PL611-30 is a low-cost general purpose frequency synthesizer and a member of PhaseLink’s Factory
Programmable ‘Quick Turn Clock (QTC)’ family. PhaseLink’s PL611-30 product family can generate any output
frequency up to 375 MHz from fundamental crystal input between 10 MHz - 30 MHz, or a 3rd overtone crystal of
up to 75Mhz. The PL611-30 produces differential CMOS outputs to support PECL, LVDS, and CMOS inputs.
BLOCK DIAGRAM
XIN/FIN
XOUT
Xtal
OSC
FRef
.
R- counter
M-counter
( 6 -bit)
Phase
Detector
Charge
Pump
FSEL
OE
CLoad
FVCO = F Ref. * (2 * M /R)
P-counter
(5-bit)
VCO
FOut = FVCO / (2 * P)
Loop
Filter
Programmable Function
/1, /2
CLK[0:1]
CLK2
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 1




PhaseLink Corporation

PL611-30 Datasheet Preview

PL611-30 Datasheet

Programmable Quick Turn Clock

No Preview Available !

PPreliminary L611-30
Programmable Quick Turn ClockTM
KEY PROGRAMMING PARAMETERS
CLK[ 0:2 ]
Output Frequency
Fout = FIN * M / (R * P)
where M= 6 bit
R= 1
P= 5 bit
1. CLK[0:1]= VCO / 2 * P
www.DataShe2et.4CU.LcKom[2]= FIN or FIN/2
Output Drive
Strength
Crystal
Load
Programmable
Input/Output (pin #7)
Std: 10mA
(default)
High: 24mA
+/- 200ppm One output pin can be
tuning.
configured as
1. CLK2 = FIN or FIN/2
2. FSEL - input
3. OE - input
# of
Register
Banks
2
Charge-Pump
Current
4 levels of pump
current setting
PIN DESCRIPTION
Name
XIN/FIN
GND
CLK[0:1]
VDD
DNC
CLK2, OE, FSEL
Pin #
(M)SOP-8
1
2
3,4
5
6
7
Type
I
P
O
P
-
B
Description
Crystal or Reference input pin
GND connection
Programmable Clock Output [note:CLK0=~CLK1]
VDD connection
Do No Connect
This programmable I/O pin can be configured as CLK2
(FIN or FIN/2) output, or OE input, or Frequency
Selection (FSEL) input pin. This pin has an internal 60K
pull up resistor.
State
0
1 (default)
OE
Tristate
CLK[0:1]
Normal
mode
FSEL
Select Bank ’0’
ROM
Select Bank ‘1’
ROM
XOUT
8 O Crystal output pin
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 2


Part Number PL611-30
Description Programmable Quick Turn Clock
Maker PhaseLink Corporation
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PL611-30 Datasheet PDF






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PhaseLink Corporation





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