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PhaseLink Corporation

PL610-01 Datasheet Preview

PL610-01 Datasheet

1MHz to 130MHz XO IC

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P(Preliminary) L610-01
1.8V to 3.3V, 1MHz to 130MHz XO IC
FEATURES
Wide frequency coverage, programmable, advanced
oscillator design.
Programmable “Odd/Even” Divider up to ÷63
Direct oscillation operation with optional
programmable features:
o Output Drive Strength (4, 8, or 16mA)
o 6-bit Odd/Even Output Divider
www.DataSheet4UIn.cpoumt Frequency:
o Fundamental Crystal: 5MHz to 130MHz
o Reference Clock: 1MHz to 130MHz
Supports CMOS or Sine Wave input clock
Output Frequency: 20kHz to 130MHz
Very low Jitter and Phase Noise
Low current consumption
Single 1.8V, 2.5V, or 3.3V ± 10% power supply
Operating temperature range from -40C to 85C
DESCRIPTION
The PL610 is a high performance general purpose
oscillator IC for outputs up to 130MHz. Designed to
fit in a small 2 x 1.3mm DFN or 3 x 3mm SOT23
package, the PL610 offers the best phase noise and
jitter performance and lowest power consumption of
any comparable IC.
In addition, there is a ‘6’ bit optional programmable
Odd/Even divider (default= ٪1), and ‘3’
programmable output drive strengths (4mA, 8mA
(default), 16mA) to choose from. The full feature set
of the PL610 makes it the most versatile XO for any
application.
PACKAGE PIN CONFIGURATION
XIN, FIN 1
6 XOUT
OE^, PDB^, CLK1 2
5 VDD
GND 3
4 CLK0
DFN-6L
(2.0mmx1.3mmx0.6mm)
OE^, PDB^, CLK1 1
6 CLK0
GND 2
5 VDD
XIN, FIN 3
4 XOUT
SOT23-6L
(3.0mmx3.0mmx1.35mm)
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 4/2/07 Page 1




PhaseLink Corporation

PL610-01 Datasheet Preview

PL610-01 Datasheet

1MHz to 130MHz XO IC

No Preview Available !

P(Preliminary) L610-01
1.8V to 3.3V, 1MHz to 130MHz XO IC
KEY PROGRAMMING PARAMETERS (Optional)
CLK[0:1]
Output Frequency
FOUT = FREF / P*
(*: P is an Odd/Even Divider)
Where P = 6 bit
www.DataSheCetL4UK.0co=mFREF, FREF/2 or FREF / P
CLK1 = FREF, FREF/2 or CLK0
Output Drive Strength
Three optional drive strengths
to choose from:
Low: 4mA
Std: 8mA (default)
High: 16mA
Programmable
Input/Output
One output pin can be configured
as:
OE - input
PDB - input
CLK1 – output
PACKAGE PIN AND DIE PAD ASSIGNMENT
Name
Pin Assignment
DFN-6L SOT23-6L Type
Description
XIN, FIN
1
3 I Crystal or Reference Clock input pin
OE, PDB,
CLK1
2
This programmable I/O pin can be configured as an Output
Enable (OE) input, Power Down input (PDB) input or CLK1
clock output. This pin has an internal 60KΩ pull up resistor
for OE and 10MΩ pull up resistor for PDB.
1 I/O
State
OE
PDB
0 Tri-state CLK Power Down Mode
1 (default) Normal mode
Normal mode
GND
CLK0
VDD
XOUT
3 2 P GND connection
4 6 O Programmable Clock Output
5 5 P VDD connection
Crystal Output pin
6 4O
Do Not Connect (DNC ) when FIN is present
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 4/2/07 Page 2


Part Number PL610-01
Description 1MHz to 130MHz XO IC
Maker PhaseLink Corporation
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PL610-01 Datasheet PDF






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