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PLL620-06 Datasheet Preview

PLL620-06 Datasheet

(PLL620-05/06/07/08/09) Low Phase Noise XO

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.com PLL620-05/-06/-07/-08/-09Low Phase Noise XO with multipliers (for 120-200MHz Fund Xtal)
t4U Universal Low Phase Noise IC’s
heeFEATURES
taS120MHz to 200MHz Fundamental Mode Crystal.
aOutput range: 120 – 200MHz (no multiplication),
.D240 – 400MHz (2x multiplier) or 480 – 700MHz
w(4x multiplier).
wHigh yield design support up to 2pF string
w capacitance at 200MHz.
CMOS (Standard drive PLL620-07 or Selectable
mDrive PLL620-06), PECL (Enable low PLL620-08
oor Enable high PLL620-05) or LVDS output
(PLL620-09).
.cSupports 3.3V-Power Supply.
Available in 16-Pin (TSSOP or 3x3mm QFN)
UNote: PLL620-06 only available in 3x3mm.
Note: PLL620-07 only available in TSSOP.
t4DESCRIPTIONS
eePLL620-05/-06/-07/-08/-09 are XO IC specifically
designed to pull high frequency fundamental
hcrystals. Their design was optimized to tolerate
higher limits of interelectrodes capacitance and
Sbonding capacitance to improve yield. It achieves
tavery low current into the crystal resulting in better
overall stability.
aBLOCK DIAGRAM
.DSEL
wwOscillator
X+ Amplifier
w et4U.comX-
PLL
(Phase
Locked
Loop)
PLL by-pass
OE
Q
Q
PIN CONFIGURATION
(Top View)
VDD
XIN
XOUT
SEL3^
SEL2^
OE
GND
GND
1
2
3
4
5
6
7
8
16 SEL0^
15 SEL1^
14 GND
13 CLKC
12 VDD
11 CLKT
10 GND
9 GND
XIN
XOUT
SEL2^
OE
12 11 10 9
13 8
14 PLL620-0x 7
15 6
16
1
23
5
4
GND
CLKC
VDD
CLKT
^: Internal pull-up
*: PLL620-06 pin 12 is output drive select (DRIVSEL)
(0 for High Drive CMOS, 1 for Standard Drive CMOS)
OUTPUT ENABLE LOGICAL LEVELS
Part #
OE
State
PLL620-08
0 (Default) Output enabled
1 Tri-state
PLL620-05
0 Tri-state
PLL620-06
PLL620-07
PLL620-09
1 (Default) Output enabled
OE input: Logical states defined by PECL levels for PLL620-08
Logical states defined by CMOS levels for PLL620-05/-06/-07/-09
www.DataShe47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 10/29/02 Page 1




PhaseLink

PLL620-06 Datasheet Preview

PLL620-06 Datasheet

(PLL620-05/06/07/08/09) Low Phase Noise XO

No Preview Available !

PLL620-05/-06/-07/-08/-09
Low Phase Noise XO with multipliers (for 120-200MHz Fund Xtal)
Universal Low Phase Noise IC’s
PIN DESCRIPTIONS
Name
TSSOP*
Pin number
3x3mm QFN*
Pin number
Type
Description
XIN 2
13 I Crystal in connector.
XOUT
3
14 I Crystal out connector.
OE 6
16 I Output enable pin.
GND
7,8,9, 10, 14
1,2,3,4,8,12
P GND (except pin 12 on PLL620-06: DRIVSEL see below).
DRIVSEL**
-
PLL620-06 only: Drive Select Input. This pin has an internal pull-
12
I
up that will default DRIVSEL to ‘1’ when not connect to GND.
CMOS output of PLL620-06 will be high drive CMOS when
DRIVSEL is set to ‘0’, and will be standard CMOS otherwise.
CLKT
11
5
O
True output PECL (PLL620-08) or LVDS (PLL620-09)
(N/C for PLL620-07)
CLKC
13
7
O
Complementary output PECL (PLL620-08) or LVDS (PLL620-09)
(CMOS out for PLL620-07).
SEL0
16
10 I
SEL1
SEL2
15
5
9 I Multiplier selector pins. These pins have an internal pull-up that
15 I will default SEL to ‘1’ when not connected to GND.
SEL3
4
Not available
I
VDD 1, 12
6,11 P +3.3V VDD.
* Note: PLL620-06 only available in 3x3mm QFN, PLL620-07 only available in TSSOP.
** Note: DRIVSEL on pin 12 on PLL620-06 only.
FREQUENCY SELECTION TABLE
SEL3
SEL2
SEL1
SEL0
10
1
1
11
1
0
11
1
1
Note: SEL3 is not available (always “1”) in 3x3mm package
All pins have internal pull-ups (default value is 1). Connect to GND to set to 0.
Selected Multiplier
Fin x 4
Fin x 2
No multiplication
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 10/29/02 Page 2


Part Number PLL620-06
Description (PLL620-05/06/07/08/09) Low Phase Noise XO
Maker PhaseLink
Total Page 8 Pages
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