Motherboard Clock Generator for AMD - K7
1 P Power supply for PLL CORE.
6 P Power supply for REF0, REF1, and crystal oscillator.
14 P Power supply for PCI (0:5).
P Power supply for SDRAM (0:12).
27 P Power supply for 24_48MHz and 48MHz.
14.318MHz crystal input that has internal loads cap (36pF) and feedback
resistor from XOUT.
5 O 14.318MHz crystal output. It has internal load cap (36pF).
Multiplexed pin controlled by MODE signal. When CPU_STOP is low, it
B will halt CPUT (0:1), CPUC0 and SDRAM (0:11) outputs. In output
mode, this pin will generate buffered reference clock output.
At power-up, MODE function will be activated. When MODE is Low, Pin
7 B 2 is input for CPU_STOP. When high, Pin 2 is output for REF0. After
input data latched, this pin will generate PCI bus clock.
At power-up, this pin is input pin and will determine CPU clock
8 B frequency. After input sampling, this pin will generate output clocks. FS3
has internal pull up (high by default).
At power-up, this pin will select 24MHz (when high) or 48MHz (when
B low) for pin25 output. After input sampling, this pin is PCI output. It has
internal pull up resistor.
O PCI clock outputs.
Buffer input pin: The signal provided to this input pin is buffered to 13
29,31,32,34,35, O SDRAM clock outputs, Fan-out Buffer outputs from SDRAMIN pin.
Serial data inputs for serial interface port.
At power-up, these pins are input pins and will determine the CPU clock
frequency. FS0, FS1 have internal pull up (high by default).
When CPU_STOP is low, this pin is still free running. When the power
down is low, this SDRAM will be stopped.
PD# 41 I When low, it will stop all clock outputs. It has internal pull-up resistor.
O “True” clocks of differential pair open-drain CPU outputs.
44 O “Complementary” clocks of differential pair open-drain CPU outputs.
48 B Buffered reference clock output after input data latched during power-up.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 03/07/00 Page 2