PLL205-01 Datasheet PDF - PhaseLink Motherboard Clock Generator Specs

PLL205-01 - Motherboard Clock Generator

Datasheet Summary

Description

P P P P P P I O B Power supply for PLL CORE.

Power supply for REF0, REF1, and crystal oscillator.

Power supply for PCI (0:5).

Features

w w.
w Generates all clock frequencies for VIA K7 chip sets requiring multiple CPU clocks and high speed SDRAM buffers. Support one pair of differential CPU clocks, one open-drain CPU, 6 PCI and 13 high-speed SDRAM buffers for 3-DIMM.

Datasheet Details

Part number	PLL205-01
Manufacturer	PhaseLink
File Size	129.31 KB
Description	Motherboard Clock Generator
Datasheet	PLL205-01 Datasheet
Additional preview pages of the PLL205-01 datasheet.

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Full PDF Text Transcription

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FEATURES • • w w• • • • • • • • w Generates all clock frequencies for VIA K7 chip sets requiring multiple CPU clocks and high speed SDRAM buffers. Support one pair of differential CPU clocks, one open-drain CPU, 6 PCI and 13 high-speed SDRAM buffers for 3-DIMM applications. One 24_48MHz clock and one 48MHz clock. Two14.318MHz reference clocks. Power management control to stop CPU, and Power down Mode from I2C programming. Support 2-wire I2C serial bus interface with builtin Vendor ID, Device ID and Revision ID. Single byte micro-step linear Frequency Programming via I2C with Glitch free smooth switching. Spread Spectrum ± 0.25% center spread, 0 to − 0.5% downspread. 50% duty cycle with low jitter. Available in 300 mil 48 pin SSOP. .D at h S a t e e 4U .

Published: Feb 9, 2006 |