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PLL205-01 Datasheet Preview

PLL205-01 Datasheet

Motherboard Clock Generator

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.com PLL205-01Motherboard Clock Generator for AMD - K7
et4UFEATURES
SheGenerates all clock frequencies for VIA K7 chip
tasets requiring multiple CPU clocks and high
aspeed SDRAM buffers.
.DSupport one pair of differential CPU clocks, one
open-drain CPU, 6 PCI and 13 high-speed
wSDRAM buffers for 3-DIMM applications.
wwOne 24_48MHz clock and one 48MHz clock.
mTwo14.318MHz reference clocks.
Power management control to stop CPU, and
oPower down Mode from I2C programming.
.cSupport 2-wire I2C serial bus interface with built-
in Vendor ID, Device ID and Revision ID.
Single byte micro-step linear Frequency Progra-
Umming via I2C with Glitch free smooth switching.
t4Spread Spectrum ±0.25% center spread, 0 to
0.5% downspread.
e50% duty cycle with low jitter.
eAvailable in 300 mil 48 pin SSOP.
hBLOCK DIAGRAM
taSXIN
aXOUT
XTAL
OSC
.DSDATA
wSCLK
FS (0:3)*
ww t4U.comPD
I2C
Logic
Control
Logic
PLL1
SST
PLL2
÷2
ataSheeSDRAMIN
VDD1
REF(0:1)
CPUT(0:1)
CPUC0
VDD2
PCI(0:4)
PCI5
VDD4
48Mhz
24_48Mhz
VDD3
SDRAM(0:11)
SDRAM12
PIN CONFIGURATION
VDD0
REF0//CPU_STOP#^
GND
XIN
XOUT
VDD1
PCI5/MODE*^
PCI0/FS3*^
GND
PCI1/SEL24_48*^
PCI2
PCI3
PCI4
VDD2
SDRAMIN
GND
SDRAM11
SDRAM10
VDD3
SDRAM9
SDRAM8
GND
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 REF1/FS2*^
47 GND
46 CPUT1
45 GND
44 CPUC0
43 CPUT0
42 VDD3
41 PD#^
40 SDRAM12
39 GND
38 SDRAM0
37 SDRAM1
36 VDD3
35 SDRAM2
34 SDRAM3
33 GND
32 SDRAM4
31 SDRAM5
30 VDD3
29 SDRAM6
28 SDRAM7
27 VDD4
26 48MHz/FS0*^
25 24_48MHz/FS1*^
Note: ^: Pull up, #: Active Low
*: Bi-directional latched at power-up
I/O MODE CONFIGURATION
MODE (Pin 7)
1 (OUTPUT)
0 (INPUT)
PIN 2
REF0
CPU_STOP
POWER GROUP
VDD0: PLL CORE
VDD1: REF(0:1), XIN, XOUT
VDD2: PCI(0:5)
VDD3: SDRAM(0:12)
VDD4: 48MHz, 24_48MHz
KEY SPECIFICATIONS
CPU Cycle to Cycle jitter: 250ps.
PCI to PCI output skew: 500ps.
CPU to CPU output skew: ±175ps
SDRAM to SDRAM output skew: 250ps.
CPU to PCI skew (CPU leads): 0 ~ 3 ns.
www.D47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 03/07/00 Page 1




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PLL205-01 Datasheet Preview

PLL205-01 Datasheet

Motherboard Clock Generator

No Preview Available !

PLL205-01
Motherboard Clock Generator for AMD - K7
PIN DESCRIPTIONS
Name
Number Type
Description
VDD0
1 P Power supply for PLL CORE.
VDD1
6 P Power supply for REF0, REF1, and crystal oscillator.
VDD2
14 P Power supply for PCI (0:5).
VDD3
19,30,36,42
P Power supply for SDRAM (0:12).
VDD4
27 P Power supply for 24_48MHz and 48MHz.
GND
3,9,16,22,
33,39,45,47
P Ground.
XIN
4
I
14.318MHz crystal input that has internal loads cap (36pF) and feedback
resistor from XOUT.
XOUT
5 O 14.318MHz crystal output. It has internal load cap (36pF).
REF0//CPU_STOP
2
Multiplexed pin controlled by MODE signal. When CPU_STOP is low, it
B will halt CPUT (0:1), CPUC0 and SDRAM (0:11) outputs. In output
mode, this pin will generate buffered reference clock output.
PCI5/MODE
At power-up, MODE function will be activated. When MODE is Low, Pin
7 B 2 is input for CPU_STOP. When high, Pin 2 is output for REF0. After
input data latched, this pin will generate PCI bus clock.
PCI0/FS3
At power-up, this pin is input pin and will determine CPU clock
8 B frequency. After input sampling, this pin will generate output clocks. FS3
has internal pull up (high by default).
PCI1/SEL24_48
10
At power-up, this pin will select 24MHz (when high) or 48MHz (when
B low) for pin25 output. After input sampling, this pin is PCI output. It has
internal pull up resistor.
PCI(2:4)
11,12,13
O PCI clock outputs.
SDRAMIN
15
I
Buffer input pin: The signal provided to this input pin is buffered to 13
SDRAM outputs.
SDRAM(0:11)
17,18,20,21,28,
29,31,32,34,35, O SDRAM clock outputs, Fan-out Buffer outputs from SDRAMIN pin.
37,38
SDATA
SCLK
23 B
Serial data inputs for serial interface port.
24 I
24_48MHz/FS1,
24MHz/FS0
25,26
B
At power-up, these pins are input pins and will determine the CPU clock
frequency. FS0, FS1 have internal pull up (high by default).
SDRAM12
40
O
When CPU_STOP is low, this pin is still free running. When the power
down is low, this SDRAM will be stopped.
PD# 41 I When low, it will stop all clock outputs. It has internal pull-up resistor.
CPUT(0:1)
43,46
O “True” clocks of differential pair open-drain CPU outputs.
CPUC0
44 O “Complementary” clocks of differential pair open-drain CPU outputs.
REF1/FS2
48 B Buffered reference clock output after input data latched during power-up.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 03/07/00 Page 2


Part Number PLL205-01
Description Motherboard Clock Generator
Maker PhaseLink
Total Page 12 Pages
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