PI7C8150B bridge equivalent, asynchronous 2-port pci-to-pci bridge.
section in the introduction Revised register description bits[31:24] offset 18h - Secondary Latency Timer Register (section 14.1.13) Revised register description for bits.
First Release of Data Sheet Correction to description for bit[0] at offset 48h. Changed from Memory Read Flow Through Disable to Memory Read Flow Through Enable. Added reset condition to offset 4Ch, bits [31:28] Revised descriptions and added orderin.
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