900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf






Pericom Semiconductor Corporation

PI74ALVCH16271 Datasheet Preview

PI74ALVCH16271 Datasheet

12-Bit To 24-Bit Registered Bus Exchanger

No Preview Available !

PI74ALVCH162711122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
12-Bit To 24-Bit Multiplexed Bus Exchanger
with 3-State Outputs
Product Features
PI74ALVCH16271 is designed for low voltage operation,
VCC = 2.3V to 3.6V
Hysteresis on all inputs
www.DataSheTeyt4pUic.caolmVOLP (Output Ground Bounce)
< 0.8V at VCC = 3.3V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
< 2.0V at VCC = 3.3V, TA = 25°C
Bus Hold retains last active bus state during 3-State,
eliminating the need for external pullup resistors
Industrial operation at –40°C to +85°C
Packages available:
– 56-pin 240 mil wide plastic TSSOP (A56)
– 56-pin 300 mil wide plastic SSOP (V56)
Logic Block Diagram
Product Description
Pericom Semiconductor’s PI74AVC series of logic circuits are
produced using the Company’s advanced 0.35 micron CMOS
technology, achieving industry leading speed.
This 12-bit to 24-bit multiplexed bus exchanger is designed for 2.3V
to 3.6V VCC operation.
The PI74ALVCH16271is intended for applications in which two
separate data paths must be multiplexed onto, or demultiplexed
from, a single data path. This device is particularly suitable as an
interface between conventional DRAMs and high-speed
microprocessors
Data is stored in the internal A-to-B registers on the low-to-high
transition of the clock (CLK) input, provided clock-enable (CLKENA)
inputs are low. Proper control of these inputs allows two sequential
12-bit words to be presented as a 24-bit word on the B port.
To maximize memory access throughput, transparent latches in
the B-to-A path allow asynchronous operation. These latches
transfer data when the latch-enable (LE) inputs are low. The select
(SEL) line selects 1B or 2B data for the A outputs. Data flow is
controlled by the active-low output enables (OEA, OEB).
To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pullup resistor, the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
1 PS8360 02/02/99




Pericom Semiconductor Corporation

PI74ALVCH16271 Datasheet Preview

PI74ALVCH16271 Datasheet

12-Bit To 24-Bit Registered Bus Exchanger

No Preview Available !

PI74ALVCH16271
1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011122233-44B5566i77t8899T0011o221122233444-55B6677i88t9900M112233u4455l66t77ip8899l00e11x2233e44d556677B8899u0011s2211E2233x44c5566h7788a99n0011g22e3344r5566w7788i99t00h112233344-55S6677t88a9900t11e2211O2233u4455t66p7788u99t0011s22
Product Pin Description
Product Pin Configuration
Pin Name
OE
CLK
SEL
CLKEN
A,1B,2B
GND
VCC
Description
Output Enable Input (Active LOW)
Clock
Select (Active Low)
Clock Enable (Active Low)
3-State Outputs
Ground
Power
www.DataSThereut4tUh.cTomables(1)
Output Enable
INPUTS
OEA
OEB
HH
HL
LH
LL
OUTPUTS
A 1B,2B
ZZ
Z Active
Active
Z
Active
Active
A to B STORAGE (OEB = L)
INPUTS
CLKENA1 CLKENA2 CLK
H HX
L X
L X
X L
X L
A
X
L
H
L
H
OUTPUTS
1B
1B0(2)
2B
2B0(2)
LX
HX
XL
AO H
OEA
LE1B
2B3
GND
2B2
2B1
VCC
A1
A2
A3
GND
A4
A5
A6
A7
A8
A9
GND
A10
A11
A12
VCC
1B1
1B2
GND
1B3
LE2B
SEL
1 56
2 55
3 54
4 53
5 52
6 51
7 50
8 49
9 48
10 47
11 56-PIN 46
12 A56 45
V56
13 44
14 43
15 42
16 41
17 40
18 39
19 38
20 37
21 36
22 35
23 34
24 33
25 32
26 31
27 30
28 29
OEB
CLKENA2
2B4
GND
2B5
2B6
VCC
2B7
2B8
2B9
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
1B8
1B7
VCC
1B6
1B5
GND
1B4
CLKENA1
CLK
B to A STORAGE (OEA = L)
INPUTS
LE SEL 1B
HXX
HXX
LHL
LHH
LLX
LLX
2B
X
X
X
X
L
H
Outputs A
AO(2)
AO(2)
L
H
L
H
Notes:
1. H = High Signal Level, L = Low Signal Level
X = Irrelevant, Z = High Impedance
= Transition, Low to High
2. Output level before the indicated steady state input
conditions were established.
2 PS8360 02/02/99


Part Number PI74ALVCH16271
Description 12-Bit To 24-Bit Registered Bus Exchanger
Maker Pericom Semiconductor Corporation
Total Page 6 Pages
PDF Download

PI74ALVCH16271 Datasheet PDF

View PDF for Mobile








Similar Datasheet

1 PI74ALVCH16270 12-Bit To 24-Bit Registered Bus Exchanger
Pericom Semiconductor Corporation
2 PI74ALVCH16271 12-Bit To 24-Bit Registered Bus Exchanger
Pericom Semiconductor Corporation





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy