PI6CV857L driver equivalent, pll clock driver.
PLL clock distribution optimized for Double Data Rate SDRAM applications. Distributes one differential clock input pair to ten differential clock output pairs. Inpu.
Distributes one differential clock input pair to ten differential clock output pairs. Inputs (CLK,CLK) and (FBIN,FB.
PI6CV857L PLL clock device is developed for registered DDR DIMM applications This PLL Clock Buffer is designed for 2.5 VDDQ and 2.5V AVDD operation and differential data input and output levels. Package options include plastic Thin Shrink Small-Outli.
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