PI6C48535-11 Datasheet | Pericom Semiconductor

Features - - - - - - - - - - - Maximum operation frequency: 500MHz 4 pair of differential LVPECL outputs Selectable CLK and crystal inputs CLK accepts LVCMOS, LVTTL input level Output Skew: 30ps (maximum) Part-to-part skew: 150ps (maximum) Propagation delay: 1.5ns (maximum) 3.3V power supply Pin-to-pin patible to ICS8535-11 Operating Temperature: -40o C to 85o C Packaging (Pb-free & Green available): - 20-pin TSSOP (L) Description The PI6C48535-11 is a high-performance low-skew LVPECL fanout buffer. PI6C48535-11 features selectable of single-ended clock or crystal inputs and translates to four LVPECL outputs. The CLK input accepts LVCMOS or LVTTL signals. The outputs are synchronized with input clock during asynchronous assertion /deassertion of CLK_EN pin. PI6C48535-11 is ideal for crystal or LVCMOS/LVTTL to LVPECL translation. Typical clock translation and distribution applications are data-munications and telemunications. Block Diagram CLK_EN D Q LE CLK Xtal1 Xtal2 0 1 Q0 n Q0 Q1 n Q1 Q2 n Q2 Q3 n Q3 Pin Diagram VEE CLK_EN CLK_SEL CLK NC Xtal1 Xtal2 NC NC VCC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Q0 NQ0 VCC Q1 NQ1 Q2 NQ2 VCC Q3 NQ3 CLK_SEL PS9738 05/27/04 PI6C48535-11 .. 3.3V Low Skew 1-to-4 Crystal/LVCMOS to LVPECL Fanout Buffer Pin Description Name VEE CLK_EN CLK_SEL CLK Xtal1, Xtal2 NC VCC Q3, n Q3 Q2, n Q2 Q1, n Q1 Q0, n Q0 Pin # 1 2 3 4 6, 7 5, 8, 9 10, 13, 18 11, 12 14, 15 16, 17 19, 20 P O O O O Type P I_PU I_PD I_PD Connect to Negative power supply Synchronizing clock enable. When high, clock outputs follow clock input. When low, Qx outputs are forced low, n Qx outputs are forced high. LVCMOS/LVTTL level with 50KΩ pull up. Clock select input. When high, selects CLK1 input. When low, selects CLK0 input. LVCMOS/LVTTL level with 50KΩ pull down. LVCMOS / LVTTL clock input Crystal input and output No internal connection. Connect to 3.3V Differential output pair, LVPECL interface level. Differential output pair, LVPECL interface level....