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Pericom Semiconductor Corporation

PI2EQX3232B Datasheet Preview

PI2EQX3232B Datasheet

Serial Re-Driver

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PI2EQX3232B
3.2Gbps, 2-Port, SATAi/m, Serial Re-Driver
Features
• Supports data rates up to 3.2Gbps on each lane
• Adjustable Transmiter De-Emphasis & Amplitude
• Adjustable Receiver Equalization
• Spectrum Reference Clock Buffer Output
• Optimized for SATAi/m applications
• Input signal level detection & output squelch on all channels
• 100-Ohm Differential CML I/O’s
• Low Power (100mW per Channel)
• Standby Mode – Power Down State
• VDD Operating Range: 1.8V +/-0.1V
• Packaging (Pb-free & Green):48-contact TQFN
Block Diagram
Description
Pericom Semiconductor’s PI2EQX3232B is a low power, signal
Re-Driver. The device provides programmable equalization,
amplication, and de-emphasis, to optimize performance over a
variety of physical mediums by reducing Inter-Symbol Interference
(ISI). PI2EQX3232B supports four 100-Ohm Differential CML
data I/O’s between the Protocol ASIC to a switch fabric, across
a backplane, or to extend the signals across other distant data
pathways on the user’s platform.
The integrated equalization circuitry provides exibility with
signal integrity of the signal before the Re-Driver. Whereas the
integrated de-emphasis circuitry provides exibility with signal
integrity of the signal after the Re-Driver.
A low-level input signal detection and output squelch function
is provided for all four channels. Each channel operates fully
independantly. When a channel is enabled (EN_x=1) and
operating, that channels input signal level (on xI+/-) determines
whether the output is enabled. If the input level of the channel
falls below the active threshold level (Vth-) then the output driver
switches off, and the pin is pulled to VDD via a high impedance
resistor. If the input level of the channel falls below the active
threshold level (Vth-) then the outputs are driven to the common
mode voltage.
In addition to providing signal re-conditioning, Pericom’s
PI2EQX3232B also provides power management Stand-by mode
operated by an Enable pin.
Pin Description
Signal Detect
CML
xI+
xI-
SEL_EQ _x
EN_x
CKIN-
CKIN+
Equalizer
Limiting
Amp
CML
xO+
xO-
Power
Management
SEL_OL_x SEL_DE_ x
-- Repeated 4 times --
Buffer
IREF
EN_ OUT-
CLK OUT+
AI+ 1
AI- 2
VDD
BO+
BO-
3
4
5
VDD 6
CI+ 7
CI- 8
VDD
DO+
DO-
VDD
9
10
11
12
GND
36 AO+
35 AO-
34 VDD
33 BI+
32 BI-
31 VDD
30 CO+
29 CO-
28 VDD
27 DI+
26 DI-
25 GND
07-0225
1
PS8889D
10/03/07




Pericom Semiconductor Corporation

PI2EQX3232B Datasheet Preview

PI2EQX3232B Datasheet

Serial Re-Driver

No Preview Available !

www.DataSheet4U.com
Pin Description
Pin #
Pin Name
1 AI+
2 AI-
36 AO+
35 AO-
33 BI+
32 BI-
4 BO+
5 BO-
7 CI+
8 CI-
14 CKIN+
15 CKIN-
30 CO+
29 CO-
27 DI+
26 DI-
10 DO+
11 DO-
41, 40, 39, 38
EN_
[A,B,C,D]
13 EN_CLK
25, Center Pad
24
22
23
47
46
16
17
GND
IREF
OUT0+
OUT1-
SEL_EQ_A
SEL_EQ_B
SEL_EQ_C
SEL_EQ_D
07-0225
PI2EQX3232B
3.2Gbps, 2-Port, SATAi/m,
Serial Re-Driver
I/O
I
I
O
O
I
I
O
O
I
I
I
I
O
O
I
I
O
O
I
I
PWR
O
O
O
I
I
I
I
Description
Positive CML Input Channel A with internal 50Ω pull down
Negative CML Input Channel A with internal 50Ω pull down
Positive CML Output Channel A internal 50Ω pull up to VDD during normal opera-
tion and 2kΩ when EN_A=0. Drives to output common mode voltage when input is
<VTH–.
Negative CML Output Channel A with internal 50Ω pull up to VDD during normal
operation and 2kΩ when EN_A=0. Drives to output common mode voltage when
input is <VTH–.
Positive CML Input Channel B with internal 50Ω pull down
Negative CML Input Channel B with internal 50Ω pull down
Positive CML Output Channel B with internal 50Ω pull up to VDD during normal
operation and 2kΩ when EN_B=0. Drives to output common mode voltage when
input is <VTH–.
Negative CML Output Channel B with internal 50Ω pull up to VDD during normal
operation and 2kΩ when EN_B=0. Drives to output common mode voltage when
input is <VTH–.
Positive CML Input Channel C with internal 50Ω pull down
Negative CML Input Channel C with internal 50Ω pull down
Differential Input Reference Clock
Positive CML Output Channel C with internal 50Ω pull up to VDD during normal
operation and 2kΩ when EN_C=0. Drives to output common mode voltage when
input is <VTH–.
Negative CML Output Channel C with internal 50Ω pull up to VDD during normal
operation and 2kΩ when EN_C=0. Drives to output common mode voltage when
input is <VTH–.
Positive CML Input Channel D with internal 50Ω pull down
Negative CML Input Channel D with internal 50Ω pull down
Positive CML Output Channel D with internal 50Ω pull up to VDD during normal
operation and 2kΩ when EN_D=0. Drives to output common mode voltage when
input is <VTH–.
Negative CML Output Channel C with internal 50Ω pull up to VDD during normal
operation and 2kΩ when EN_D=0. Drives to output common mode voltage when
input is <VTH–.
Active HIGH LVCMOS signal input pins, when HIGH, it enables the CML output.
When LOW, it disables the CML output (x0+, x0-) to HI-z state. Both x0+ & x0- out-
puts will be pulled up to VDD by internal 2kΩ resistor.
Active HIGH LVCMOS signal input pin. When HIGH, it enables the OUTx+/OUTx-
outputs. When LOW, it disables these outputs, with 50Ω to ground termination.
Supply Ground
External 475Ω resistor connection to set the differential output current
Differential Reference Clock Output
Selection pins for equalizer (see Amplier Conguration Table)
w/ 50kΩ internal pull up
2
PS8889D
10/03/07


Part Number PI2EQX3232B
Description Serial Re-Driver
Maker Pericom Semiconductor Corporation
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