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Pericom Semiconductor Corporation

PI2EQX3202B Datasheet Preview

PI2EQX3202B Datasheet

Serial Re-Driver

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PI2EQX3202B
3.2Gbps, 4 Differential Channel, Serial Re-Driver
with Equalization, De-emphasis, and Squelch
Features
• Supports data rates up to 3.2Gbps on each lane
• Optimized for SATA i/m operation
• Adjustable Transmiter De-Emphasis & Amplitude
• Adjustable Receiver Equalization
• Two Spread Spectrum Reference Clock Buffer Outputs
• Optimized for SATA applications
• Input signal level detection & output squelch on all channels
• 100-Ohm Differential CML I/O’s
• Low Power (100mW per Channel)
• Standby Mode – Power Down State
• VDD Operating Range: 1.5V to 1.8V
• Packaging (Pb-free & Green): 84-ball LFBGA (NB84)
Description
Pericom Semiconductor’s PI2EQX3202B is a low power, signal
Re-Driver. The device provides programmable equalization,
amplication, and de-emphasis by using 7 select bits, SEL[0:6],
to optimize performance over a variety of physical mediums by
reducing Inter-symbol Interference. PI2EQX3202B supports four
100-Ohm Differential CML data I/O’s between the Protocol ASIC
to a switch fabric, across a backplane, or to extend the signals
across other distant data pathways on the user’s platform.
The integrated equalization circuitry provides exibility with
signal integrity of the signal before the Re-Driver. Whereas the
integrated de-emphasis circuitry provides exibility with signal
integrity of the signal after the Re-Driver.
A low-level input signal detection and output squelch function
is provided for all four channels. Each channel operates fully
independently. When a channel is enabled (EN_x=1) and
operating, that channels input signal level (on xI+/-) determines
whether the output is enabled. If the input level of the channel
falls below the active threshold level (Vth-) then the outputs are
driven to the common mode voltage.
In addition to providing signal re-conditioning, Pericom’s
PI2EQX3202B also provides power management Stand-by mode
operated by an Enable pin.
Block Diagram
CML
xI+
xI-
SEL [0:2]
EN_x
CKIN-
CKIN+
Signal Detection
LVCMOS
SD_x
Equalizer
Limiting
Amp
CML
xO+
xO-
Power
Management
SEL [2]_ x SEL [3]_ x
-- Repeated 2 times --
Buffer
IREF
OUT-
EN_ OUT+
CLK
Pin Description
1 2 3 4 5 6 7 8 9 10
A SD_C SD_D SEL0_A SEL0_B SEL4_A SEL4_B SEL6_A SEL6_B EN_A EN_B
B VDD
SD_B
VDD SEL1_A SEL2_A SEL3_A SEL5_A VDD
EN_C
VDD
C BO+
SD_A
AI+ SEL1_B SEL2_B SEL3_B SEL5_B
BI+
EN_D AO+
D BO–
VDD
AI–
E GND VDD GND
F VDD GND VDD
G DO+ SEL0_C CI+
84-Ball LFBGA
BI–
GND
AO–
GND
GND
GND
VDD GND VDD
DI+ SEL6_C CO+
H DO– SEL0_D CI–
VDD CKIN+ CKIN– GND
DI– SEL6_D CO–
J GND SEL1_C GND SEL2_C SEL2_D SEL3_D IREF
GND SEL4_D GND
K EN_CLK SEL1_D SEL3_C SEL4_C OUT0+ OUT0– OUT1+ OUT1– SEL5_C SEL5_D
08-0103
1
PS8885G
04/30/08




Pericom Semiconductor Corporation

PI2EQX3202B Datasheet Preview

PI2EQX3202B Datasheet

Serial Re-Driver

No Preview Available !

www.DataSheet4U.com
PI2EQX3202B
3.2Gbps, 4 Differential Channel, Serial Re-Driver
with Equalization, De-emphasis, and Squelch
Pin Description
Pin #
B1, F1, D2, E2,
B3, F3, H4, B8,
F8, B10, F10
Pin Name
VDD
C3 AI+
D3 AI-
E1, J1, F2, E3,
J3, H7, E8, J8,
D9, E9, F9, E10,
J10
GND
C8 BI+
D8 BI-
G3 CI+
H3 CI-
G8 DI+
H8 DI-
A3, B4, B5 SEL[0:2]_A
A4, C4, C5 SEL[0:2]_B
G2, J2, J4
SEL[0:2]_C
H2, K2, J5 SEL[0:2]_D
B6, A5
SEL[3:4]_A
C6, A6
SEL[3:4]_B
K3, K4
SEL[3:4]_C
J6, J9
SEL[3:4]_D
B7, A7
SEL[5:6]_A
C7, A8
SEL[5:6]_B
K9, G9
SEL[5:6]_C
K10, H9
SEL[5:6]_D
C10 AO+
D10 AO-
C1 BO+
D1 BO-
G10 CO+
H10 CO-
G1 DO+
H1 DO-
A9, A10, B9, C9
EN_
[A,B,C,D]
I/O Description
PWR Supply Voltage, 1.5V to 1.8V ± 0.1V
I CML Input Channel A with internal 50Ω pull down
PWR Supply Ground
I CML Input Channel B with internal 50Ω pull down
I CML Input Channel C with internal 50Ω pull down
I CML Input Channel D with internal 50Ω pull down
I
I Selection pins for equalizer (see Amplier Conguration Table)
I w/ 50kΩ internal pull up
I
I
I Selection pins for amplier (see Amplier Conguration Table)
I w/ 50kΩ internal pull up
I
I
I Selection pins for De-Emphasis (See De-Emphasis Conguration Table)
I w/ 50kΩ internal pull up
I
O
CML Output Channel A internal 50Ω pull up to VDD during normal operation and
2kΩ when EN_A=0. Drives to output common mode voltage when input is <VTH–.
CML Output Channel B with internal 50Ω pull up to VDD during normal opera-
O tion and 2kΩ when EN_B=0. Drives to output common mode voltage when input is
<VTH–.
CML Output Channel C with internal 50Ω pull up to VDD during normal opera-
O tion and 2kΩ when EN_C=0. Drives to output common mode voltage when input is
<VTH–.
CMLOutput Channel D with internal 50Ω pull up to VDD during normal opera-
O tion and 2kΩ when EN_D=0. Drives to output common mode voltage when input is
<VTH–.
Active HIGH LVCMOS signal input pins, when HIGH, it enables the CML output.
I When LOW, it disables the CML output (x0+, x0-) to HI-z state. Both x0+ & x0- out-
puts will be pulled up to VDD by internal 2kΩ resistor.
(Continued)
08-0103
2
PS8885G
04/30/08


Part Number PI2EQX3202B
Description Serial Re-Driver
Maker Pericom Semiconductor Corporation
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