PT7C4512 - PLL Clock Multiplier

Description

Zero ppm multiplication error Input crystal frequency of 5 - 40 MHz Input clock frequency of 4 - 50 MHz Output clock frequencies up to 200 MHz Low period jitter 80ps (100~200MHz) Duty cycle of 45/55% of output clock up to 160MHz 9 selectable frequencies con

Pericom Semiconductor

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Datasheet Details

Part number	PT7C4512
Manufacturer	Pericom Semiconductor
File Size	221.72 KB
Description	PLL Clock Multiplier
Datasheet	PT7C4512 Datasheet
Additional preview pages of the PT7C4512 datasheet.

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Full PDF Text Transcription

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PT7C4512 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| PLL Clock Multiplier Features Description  Zero ppm multiplication error  Input crystal frequency of 5 - 40 MHz  Input clock frequency of 4 - 50 MHz  Output clock frequencies up to 200 MHz  Low period jitter 80ps (100~200MHz)  Duty cycle of 45/55% of output clock up to 160MHz  9 selectable frequencies controlled by S0, S1 pins  Operating voltages of 3.0 to 5.

Published: Jun 2, 2016 |