PI6LC48P02 Datasheet | Pericom Semiconductor

2-Output LVPECL Fibre Channel (FC) and Ethernet Clock Generator Features ÎÎTwo differential LVPECL output pairs ÎÎSelectable crystal oscillator interface or LVCMOS/LVTTL single-ended clock input ÎÎSupports the following output frequencies: ÎÎEthernet: 50MHz, 100MHz, 150MHz, 156.25MHz, 200MHz ÎÎFibre Channel: 53.125MHz, 106.25MHz, 159.375MHz, 187.5MHz, 212.5MHz ÎÎRMS phase jitter @ 212.5MHz, using a 26.5625MHz crystal (12k Hz - 20MHz): 0.28ps (typical) ÎÎRMS phase jitter @ 100MHz, using a 25MHz crystal (12k Hz - 20MHz): 0.32ps (typical) ÎÎRMS phase jitter @ 156.25MHz, using a 26.041667MHz crystal (12k Hz - 20MHz): 0.30ps (typical) ÎÎFull 3.3V or 2.5V supply modes ÎÎIndustrial operating temperature ÎÎAvailable in lead-free package: 20-TSSOP Description The PI6LC48P02 is a 2-output LVPECL synthesizer optimized to generate Fibre Channel, Ethernet and storage reference clock frequencies and is a member of Peri’s Hi Flex family of high performance clock solutions. Using a 26.5625MHz crystal, the most popular Fibre Channel (FC) frequencies can be generated based on the settings of 2 frequency select pins. Using 25MHz Xtal, most Ethenrnet frequencies inckuding 100MHz can be generated, while using 26.041667MHz Xtal, 156.25MHz can be generated for Networking applications. The PI6LC48P02 uses Peri’s proprietary low phase noise PLL technology to achieve ultra low phase jitter, it is ideal for Networking, data center, and storage systems. Applications ÎÎNetworking and Data Center Server systems ÎÎFibre Channel (FC) and Storage systems Block Diagram XTAL_IN XTAL_OUT Ref_IN IN_SEL M_reset PFD VCO M PLL_By Pass N_SEL[0:1] /N CLK0 CLK0# CLK1 CLK1# 15-0102 1 .peri. Rev....