PI3VDP3212 Datasheet | Pericom Semiconductor

2-Lane Display Port™ Rev 1.2 pliant Switch Features ÎÎ2-lane, 1:2 mux/demux that will support RBR, HBR1, or HBR2 ÎÎ1-channel 1:2 mux/demux for DP_HPD signal ÎÎ1-differential channel 1:2 mux/demux for DP_Aux signal with support up to 720Mbps ÎÎInsertion Loss for high speed channels @ 2.7 GHz: -1.7d B ÎÎ-3d B Bandwidth for high speed channels: 4.7GHz ÎÎReturn loss for high speed channels @ 2.7GHz: -16d B ÎÎLow Bit-to-Bit Skew , 7ps max (between '+' and '-' bits) ÎÎLow Crosstalk for high speed channels: -25d B@5.4 Gbps ÎÎLow Off Isolation for high speed channels: -25d B@5.4 Gbps ÎÎVDD Operating Range: 3.3V +/-10% ÎÎESD Tolerance: 2k V HBM ÎÎLow channel-to-channel skew, 35ps max ÎÎPackaging (Pb-free & Green): àà 32 TQFN (ZL) Description Peri Semiconductor’s PI3VDP3212 mux/demux is targeted for next generation digital video signals. This device can be used to connect a Display Port™ Source to two Independent Display Port Sinks or to connect two Display Port sources to a single DP display. The newly released Display Port spec requires a data rate of 5.4 Gbps. Peri's solution has been specifically designed around this standard and will support such signals. Application Routing of Display Port signals with low signal attenuation between source and sink. Block Diagram D0+ D0 - D1+ D1 - D0+A D0-A D1+A D1-A 13-0166 AUX+ AUX- OE SEL AUX_SEL Logic Control D0+B D0-B D1+B D1-B AUX+ A AUX-A HPD A AUX+ B AUX- B HPD B 11/11/13 2-Lane Display Port™ Rev 1.2 pliant Switch Pin Assignment (TQFN-32) D0+ D0VDD D1+ D1AUX+ AUXHPD VDD SEL OE 1 2 3 4 5 6 7 8 9 10 11 32 31 30 29 28 AUX_SEL D0+A D0-A VDD GND 27 D1+A 26 D1-A 25 D0+B 24 D0-B 23 D1+B 22 D1-B 21 GND 20 VDD 19 AUX+A 18 AUX-A 17 HPD_A Truth Table AUX_ OE SEL SEL...