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Pericom Semiconductor

PI2EQX3202 Datasheet Preview

PI2EQX3202 Datasheet

Serial Re-driver

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PI2EQX3202
3.2Gbps, 4 Differential Channel, Serial Re-driver
with Built-in Equalization & De-emphasis
Features
• Supports data rates up to 3.2Gbps on each lane
• Adjustable Transmiter De-Emphasis & Amplitude
• Adjustable Receiver Equalization
• Two Spread Spectrum Reference Clock Buffer Outputs
• 100Ω Differential CML I/O’s
• Low Power (100mW per Channel)
• Standby Mode – Power Down State
• VCC Operating Range: 1.8V +/-0.1V
• Packaging (Pb-free & Green):
- 84-ball LFBGA
Description
Pericom Semiconductor’s PI2EQX3202 is a low power, signal
re-driver. The device provides programmable equalization,
amplification, and de-emphasis by using 7 select bits, SEL[0:6],
to optimize performance over a variety of physical mediums by
reducing Inter-symbol interference. PI2EQX3202 supports four
100 Differential CML data I/O’s between the Protocol ASIC to
a switch fabric, across a backplane, or extends the signals across
other distant data pathways on the user’s platform.
The integrated equalization circuitry provides flexibility with
signal integrity of the signal before the re-driver. Whereas the
integrated de-emphasis circuitry provides flexibility with signal
integrity of the signal after the re-driver.
In addition to providing signal re-conditioning, Pericom’s
PI2EQX3202 also provides power management Stand-by mode
operated by a Bus Enable pin.
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Block Diagram
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Pin Description
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06-0087
1
PS8819
02/28/06




Pericom Semiconductor

PI2EQX3202 Datasheet Preview

PI2EQX3202 Datasheet

Serial Re-driver

No Preview Available !

PI2EQX3202
3.2Gbps, 4 Differential Channel, Serial Re-driver
with Built-in Equalization & De-emphasis
Pin Description
Pin #
Pin Name
B1, F1, D2, E2,
B3, F3, H4, B8,
F8, B10, F10
VDD
C3 AI+
D3 AI-
E1, J1, F2, E3,
J3, H7, E8, J8,
D9, E9, F9, E10,
J10
GND
C8 BI+
D8 BI-
G3 CI+
H3 CI-
G8 DI+
H8 DI-
A3, B4, B5 SEL[0:2]_A
A4, C4, C5 SEL[0:2]_B
G2, J2, J4
SEL[0:2]_C
H2, K2, J5 SEL[0:2]_D
B6, A5
SEL[3:4]_A
C6, A6
SEL[3:4]_B
K3, K4
SEL[3:4]_C
J6, J9
SEL[3:4]_D
B7, A7
SEL[5:6]_A
C7, A8
SEL[5:6]_B
K9, G9
SEL[5:6]_C
K10, H9
SEL[5:6]_D
C10 AO+
D10 AO-
C1 BO+
D1 BO-
G10 CO+
H10 CO-
G1 DO+
H1 DO-
I/O Description
PWR 1.8V Supply Voltage
I Positive CML Input Channel A with internal 50Ω pull down
I Negative CML Input Channel A with internal 50Ω pull down
PWR Supply Ground
I Positive CML Input Channel B with internal 50Ω pull down
I Negative CML Input Channel B with internal 50Ω pull down
I Positive CML Input Channel C with internal 50Ω pull down
I Negative CML Input Channel C with internal 50Ω pull down
I Positive CML Input Channel D with internal 50Ω pull down
I Negative CML Input Channel D with internal 50Ω pull down
I
I Selection pins for equalizer (see Amplifier Configuration Table)
I w/ 50KΩ internal pull up
I
I
I Selection pins for amplifier (see Amplifier Configuration Table)
I w/ 50KΩ internal pull up
I
I
I Selection pins for De-Emphasis (See De-Emphasis Configuration Table)
I w/ 50KΩ internal pull up
I
O
Positive CML Output Channel A internal 50Ω pull up during normal operation and
2KΩ pull up otherwise.
O
Negative CML Output Channel A with internal 50Ω pull up during normal operation
and 2KΩ pull up otherwise.
O
Positive CML Output Channel B with internal 50Ω pull up during normal operation
and 2KΩ pull up otherwise.
O
Negative CMLOutput Channel B with internal 50Ω pull up during normal operation
and 2KΩ pull up otherwise.
O
Positive CMLOutput Channel C with internal 50Ω pull up during normal operation
and 2KΩ pull up otherwise.
O
Negative CMLOutput Channel C with internal 50Ω pull up during normal operation
and 2KΩ pull up otherwise.
O
Positive CMLOutput Channel D with internal 50Ω pull up during normal operation
and 2KΩ pull up otherwise.
O
Negative CMLOutput Channel D with internal 50Ω pull up during normal operation
and 2KΩ pull up otherwise.
06-0087
2
PS8819
02/28/06


Part Number PI2EQX3202
Description Serial Re-driver
Maker Pericom Semiconductor
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PI2EQX3202 Datasheet PDF






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