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Peregrine Semiconductor

PE42850 Datasheet Preview

PE42850 Datasheet

UltraCMOS SP5T RF Switch

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Product Description
The PE42850 is a HaRP™ technology-enhanced SP5T
high power RF switch supporting wireless applications up
to 1 GHz. It offers maximum power handling of 42.5 dBm
continuous wave (CW). It delivers high linearity and
excellent harmonics performance. It has both a standard
and attenuated RX mode. No blocking capacitors are
required if DC voltage is not present on the RF ports.
The PE42850 is manufactured on Peregrine’s
UltraCMOS® process, a patented variation of silicon-on-
insulator (SOI) technology on a sapphire substrate,
offering the performance of GaAs with the economy and
integration of conventional CMOS.
Figure 1. Package Type
32-lead 5 × 5 mm QFN
Product Specification
PE42850
UltraCMOS® SP5T RF Switch
30–1000 MHz
Features
 Dual mode operation: SP5T or SP3T
 HaRP™ technology enhanced
 Fast settling time
 No gate and phase lag
 No drift in insertion loss and phase
 Up to 45 dBm instantaneous power
in 50
 Up to 40 dBm instantaneous power
< 8:1 VSWR
 36 dB TX to RX isolation
 Low harmonics of 2fo and 3fo = –90 dBc
(1.15:1 VSWR)
 ESD performance
 1.5 kV HBM on all pins
Figure 2. Functional Diagram of SP3T
Configuration
Figure 3. Functional Diagram of SP5T
Configuration
ANT can be tied to TX1 and TX2 or TX3 and TX4
Document No. DOC-81084-1 www.psemi.com
SP5T, standard configuration
DOC-02178
©2012-2016 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 12




Peregrine Semiconductor

PE42850 Datasheet Preview

PE42850 Datasheet

UltraCMOS SP5T RF Switch

No Preview Available !

PE42850
Product Specification
Table 1.
Electrical Specifications
VSS_EXT = –3.4V (ZS = ZL =
@ –40 to +85
50), unless
o°Cth, eVrDwDis=e2n.3o–t5e.d51V,
VSS_EXT
=
0V
or
VDD
=
3.4–5.5V,
Parameter
Path
Condition
Min Typ Max Unit
Operating frequency
30 1000 MHz
Insertion loss2
ANT–TX
Active TX port 1, 2, 3 or 4 @ rated power (–40 °C, +25 °C)
30–520 MHz
520–1000 MHz
Active TX port 1, 2, 3 or 4 @ rated power (+85 °C)
30–520 MHz
520–1000 MHz
0.25
0.35
0.30
0.45
0.30
0.45
0.35
0.55
dB
dB
dB
dB
Insertion loss2
(un-attenuated state)
ANT–RX
Active RX port (–40 °C, +25 °C)
30–520 MHz
520–1000 MHz
Active RX port (+85 °C)
30–520 MHz
520–1000 MHz
0.50
0.65
0.60
0.70
0.60
0.80
0.70
0.85
dB
dB
dB
dB
1575 MHz for GPS RX, < –10 dBm, +25 °C
1 1.2 dB
Insertion loss2 (attenuated state)
ANT–RX
Active RX port
30–1000 MHz
15.2 16 16.8 dB
Isolation (supply biased)
Isolation (supply biased)
Unbiased isolation
VDD, V1, V2, V3 = 0V
Unbiased isolation
VDD, V1, V2, V3 = 0V
Return loss2
TX–TX
TX–RX
30–520 MHz
520–1000 MHz
30–520 MHz
520–1000 MHz
ANT–TX +27 dBm
ANT–RX +27 dBm
ANT–RX
Un-attenuated state
30–520 MHz
520–1000 MHz
Un-attenuated state, 1575 MHz for GPS RX, < –10 dBm, +25 °C
33
29
34
29
6
14
22
18
10
36
30
36
30
27
22
14
dB
dB
dB
dB
dB
dB
dB
dB
dB
Attenuated state, optimized without attenuator engaged
30–520 MHz
520–1000 MHz
16 21
13 18
dB
dB
Return loss2
ANT–TX
30–520 MHz
520–1000 MHz
21 28
15 17
dB
dB
2nd and 3rd harmonic
(< 1.15:1 VSWR)
30–520 MHz @ +40.0 dBm
TX 521–870 MHz @ +38.5 dBm
871–1000 MHz @ +37.5 dBm
–90 –81 dBc
2nd and 3rd harmonic
(< 8:1 VSWR)
30–520 MHz @ +40.0 dBm (pulsed signal, at 10% duty cycle3)
TX 521–870 MHz @ +38.5 dBm (pulsed signal, at 10% duty cycle3)
871–1000 MHz @ +37.5 dBm (pulsed signal, at 10% duty cycle3)
–82 –74 dBc
2nd and 3rd harmonic
(50source/load impedance)
TX 30–1000 MHz @ +45.0 dBm (pulsed signal, at 10% duty cycle3)
–80 –71 dBc
2nd and 3rd harmonic
(50source/load impedance)
TX 30–1000 MHz @ +42.5 dBm (CW)
–84 –75 dBc
Input 0.1dB compression point4 ANT–TX 1000 MHz
45.5 dBm
IIP3
RX
Un-attenuated state
Attenuated state
42 dBm
33 dBm
Settling time
From 50% control until harmonics within specifications
30 70 µs
Switching time
50% CTRL to 90% or 10% RF
15 µs
Notes: 1. In a 2TX–1RX SP3T configuration, TX1 and TX2 are tied and TX3 and TX4 are tied respectively. Refer to Application Note AN35 for SP3T performance data.
2. Narrow trace widths are used near each port to improve impedance matching. Refer to evaluation board layouts (Figure 23) and schematic (Figure 24) for details.
3. 10% of 4620 µs period.
4. The input 0.1dB compression point is a linearity figure of merit. Refer to Table 3 for the RF input power PIN.
©2012-2016 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 12
Document No. DOC-81084-1 UltraCMOS® RFIC Solutions


Part Number PE42850
Description UltraCMOS SP5T RF Switch
Maker Peregrine Semiconductor
Total Page 12 Pages
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