include intermittent operation by the power save (PS) control signal and high-speed pull-in that rapidly corrects the phase differences occurring at the start of operation. Pin Assignment
XIN XOUT FV VDD DOP VSS LD FIN
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
OR OV LC FR PS LE DATA CLK
Features
Low power supply voltage: VDD =1.8 to 2.5V Low power consumption: 5mW (VDD =2.0V, FIN =100MHz) High-speed operation: FIN =175MHz Frequency dividing ratios in reference frequency dividing stage: 5 to 1.