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PM73123 - 8 Link CES/DBCES AAL1 SAR

Download the PM73123 datasheet PDF. This datasheet also covers the PM73123_PMC variant, as both devices belong to the same 8 link ces/dbces aal1 sar family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • Supports eight structured/unstructured T1, E1 links or one unstructured DS3, E3 or STS-1/STM-0 link over an AAL1 CBR ATM network.
  • Compliant with ATM Forum's CES (AFVTOA-0078), and ITU-T I.363.1.
  • Supports up to 256 VCs.
  • Supports n x 64 (consecutive channels) and m x 64 (nonconsecutive channels) structured data format with channel associated signaling (CAS) support.
  • Internal E1/T1 clock synthesizers provided for each line which can be controlled vi.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (PM73123_PMC-Sierra.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number PM73123
Manufacturer PMC-Sierra
File Size 55.62 KB
Description 8 Link CES/DBCES AAL1 SAR
Datasheet download datasheet PM73123 Datasheet

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Other Datasheets by PMC-Sierra

Part Number Description
PM73121 AAL1 Segmentation And Reassembly Processor
PM73122 32 LINK CES/DBCES AAL1 SAR PROCESSOR
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PM7323 ATM LAYER ROUTING CONTROL
PM7324 SATURN USER NETWORK INTERFACE ATM LAYER SOLUTION

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
PM73123 www.DataSheet4U.com AAL1gator™-8 8 Link CES/DBCES AAL1 SAR FEATURES • Supports eight structured/unstructured T1, E1 links or one unstructured DS3, E3 or STS-1/STM-0 link over an AAL1 CBR ATM network. • Compliant with ATM Forum's CES (AFVTOA-0078), and ITU-T I.363.1. • Supports up to 256 VCs. • Supports n x 64 (consecutive channels) and m x 64 (nonconsecutive channels) structured data format with channel associated signaling (CAS) support. • Internal E1/T1 clock synthesizers provided for each line which can be controlled via internal synchronous residual time stamp (SRTS) or an internal programmable weighted moving average adaptive clocking algorithm in unstructured mode.