PCS3P623Z05B ic equivalent, peak emi reduction ic.
* Clock Distribution with Timing−Safe Peak EMI Reduction
* Input Frequency Range: 20 MHz − 50 MHz
* Multiple Low Skew Timing−Safe Outputs:
PCS3P623Z05: 5 Outp.
requiring zero input−output delay, all outputs, including DLY_CTRL, must be equally loaded. Even if DLY_CTRL is not used.
PCS3P623Z05/09 is a versatile, 3.3 V Zero−delay buffer designed
to distribute Timing−Safe clocks with Peak EMI reduction. PCS3P623Z05 is an eight−pin version, accepts one reference input and drives out five low−skew Timing−Safe clocks. PCS3P623Z09 ac.
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