PCS3P622Z09B Datasheet | onsemi

Description PCS3P622Z05/09 is a versatile, 3.3 V Zero- delay buffer designed to distribute low frequency Timing- Safe clocks with Peak EMI reduction. PCS3P622Z05 is an eight- pin version, accepts one reference input and drives out five low- skew Timing- Safe clocks. PCS3P622Z09 accepts one reference input and drives out nine low- skew Timing- Safe clocks. PCS3P622Z05/09 has a DLY_CTRL for adjusting the Input- Output clock delay, depending upon the value of capacitor connected at this pin to GND. PCS3P622Z05/09 operates from a 3.3 V supply and is available in two different packages, as shown in the ordering information table, over mercial and Industrial temperature range. Application PCS3P622Z05/09 is targeted for use in Displays and memory interface systems. Features - Low Frequency Clock Distribution with Timing- Safe Peak EMI Reduction - Input Frequency Range: 4 MHz - 20 MHz - Multiple Low Skew Timing- Safe Outputs: PCS3P622Z05: 5 Outputs PCS3P622Z09: 9 Outputs - External Input- Output Delay Control Option - Supply Voltage: 3.3 V ± 0.3 V - mercial and Industrial Temperature Range - Packaging Information: ASM3P622Z05: 8 pin SOIC, and TSSOP ASM3P622Z09: 16 pin SOIC, and TSSOP - True Drop- in Solution for Zero Delay Buffer, ASM5P2305A / 09A - These Devices are Pb- Free, Halogen Free/BFR Free and are Ro HS pliant This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. http://onsemi. TSSOP- 8 T SUFFIX CASE 948AL SOIC- 8 S SUFFIX CASE 751BD TSSOP- 16 T SUFFIX CASE 948AN SOIC- 16 S SUFFIX CASE 751BG ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet. © Semiconductor ponents Industries, LLC, 2011 August, 2011 - Rev. P2 Publication Order Number: PCS3P622Z05/D PCS3P622Z05B, PCS3P622Z05C, PCS3P622Z09B, PCS3P622Z09C CLKIN PCS3P622Z05B/C CLKIN PLL MUX DLY_CTRL CLKOUT1 CLKOUT2 CLKOUT3...