* Low Frequency Clock Distribution with Timing−Safe Peak EMI Reduction
* Input Frequency Range: 4 MHz − 20 MHz
* Multiple Low Skew Timing−Safe Outputs: PCS3P6.

requiring zero input−output delay, all outputs, including DLY_CTRL, must be equally loaded. Even if DLY_CTRL is not used.

PCS3P622Z05/09 is a versatile, 3.3 V Zero−delay buffer designed to distribute low frequency Timing−Safe clocks with Peak EMI reduction. PCS3P622Z05 is an eight−pin version, accepts one reference input and drives out five low−skew Timing−Safe clocks. .

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