Datasheet4U Logo Datasheet4U.com

P3P622S01J - Peak EMI Reduction IC

General Description

P3P622S01J is a versatile, 3.3 V Zero delay buffer designed to distribute low frequency Timing

Safe Clocks with Peak EMI Reduction.

P3P622S01J accepts an input clock either from a fundamental Crystal or from an external reference clock.

Key Features

  • Low Frequency Clock Distribution with Timing.
  • Safe Peak EMI Reduction.
  • Input Frequency Range: 4 MHz.
  • 20 MHz.
  • Zero Input.
  • Output Propagation Delay.
  • Low.
  • skew Outputs:.
  • Output.
  • output Skew Less than 250 pS.
  • Device.
  • device Skew Less than 700 pS.
  • Less than 200 pS Cycle.
  • to.
  • cycle Jitter.
  • Available in 8 Pin, 4.4 mm TSSOP Package.
  • Supply Voltage: 3.3 V ± 0.3 V.

📥 Download Datasheet

Datasheet Details

Part number P3P622S01J
Manufacturer onsemi
File Size 131.14 KB
Description Peak EMI Reduction IC
Datasheet download datasheet P3P622S01J Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
P3P4GF4BLF 4G Bits Die DDRIII SDRAM Deutron Electronics

Other Datasheets by onsemi

Part Number Description
P3P623S00B Peak EMI Reduction IC
P3P623S00E Peak EMI Reduction IC
P3P623S05A Timing-Safe Peak EMI Reduction IC
P3P623S05B Timing-Safe Peak EMI Reduction IC
P3P623S09A Timing-Safe Peak EMI Reduction IC

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
P3P622S01J Timing-Safet Peak EMI Reduction IC Functional Description P3P622S01J is a versatile, 3.3 V Zero−delay buffer designed to distribute low frequency Timing−Safe Clocks with Peak EMI Reduction. P3P622S01J accepts an input clock either from a fundamental Crystal or from an external reference clock. P3P622S01J accepts one reference input and drives out two low−skew clocks. P3P622S01J has an on−chip PLL that locks to an input reference clock. The PLL feedback is on−chip and is obtained from the CLKOUT pad, internal to the device. Multiple P3P622S01J devices can accept the same input clock and distribute it. In this case, the skew between the outputs of the two devices is guaranteed to be less than 700 pS. The output has less than 200 pS of cycle−to−cycle jitter.