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  ON Semiconductor Electronic Components Datasheet  

NB7VQ58M Datasheet

1.8V / 2.5V / 3.3V Differential 2:1 Clock/Data Multiplexer / Translator

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NB7VQ58M
1.8V / 2.5V / 3.3V
Differential 2:1 Clock/Data
Multiplexer / Translator
with CML Outputs
w/ Selectable Input Equalizer
MultiLevel Inputs w/ Internal Termination
http://onsemi.com
MARKING
DIAGRAM*
16
Description
The NB7VQ58M is a high performance differential 2to1 Clock or
Data multiplexer with a selectable Equalizer receiver. When placed in
series with a Clock /Data path operating up to 7 GHz or 10.7 Gb/s,
respectively, the NB7VQ58M inputs will compensate the degraded
signal transmitted across an FR4 PCB backplane or cable
interconnect. Therefore, the serial data rate is increased by reducing
InterSymbol Interference (ISI) caused by losses in copper
interconnect or long cables.
1
QFN16
MN SUFFIX
CASE 485G
A
L
Y
W
G
1
NB7V
Q58M
ALYW G
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= PbFree Package
The EQualizer ENable pin (EQEN) allows the INn/INn inputs to
either flow through or bypass the Equalizer section. Control of the
Equalizer function is realized by setting EQEN; When EQEN is set
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Low, the INn / INn inputs bypass the Equalizer. When EQEN is set
High, the INn / INn inputs flow through the Equalizer. The default
SIMPLIFIED BLOCK DIAGRAM
state at startup is LOW. As such, the NB7VQ58M is ideal for SONET,
GigE, Fiber Channel, Backplane and other Clock/Data distribution
applications.
The differential inputs incorporate internal 50 W termination
resistors that are accessed through the VT pin. This feature allows the
NB7VQ58M to accept various logic level standards, such as LVPECL,
www.DatCaSMheLeot4rUL.cVoDmS.
The NB7VQ58M produces minimal Clock or Data jitter operating
up to 7 GHz or 10.7 Gb/s, respectively.
The 16 mA differential CML outputs provide matching internal
50 W terminations and 400 mV output swings when externally
terminated with a 50 W resistor to VCC.
The NB7VQ58M is offered in a low profile 3mm x 3 mm 16pin
VCC
EQ
QFN package and is a member of the GigaCommfamily of high
performance Clock / Data products. Application notes, models, and
support documentation are available at www.onsemi.com.
Features
Maximum Input Data Rate > 10.7 Gb/s
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
Data Dependent Jitter < 15 ps
Maximum Input Clock Frequency > 7 GHz
Differential CML Outputs, 400 mV PeaktoPeak,
Random Clock Jitter < 0.8 ps RMS
Selectable Input Equalization
180 ps Typical Propagation Delay
35 ps Typical Rise and Fall Times
Typical
Operating Range: VCC = 1.71 V to 3.6 V with GND =
0V
Internal 50 W Input Termination Resistors
This is a PbFree Device
© Semiconductor Components Industries, LLC, 2009
August, 2009 Rev. 0
1
Publication Order Number:
NB7VQ58M/D


  ON Semiconductor Electronic Components Datasheet  

NB7VQ58M Datasheet

1.8V / 2.5V / 3.3V Differential 2:1 Clock/Data Multiplexer / Translator

No Preview Available !

NB7VQ58M
IN0 1
IN0 2
IN1 3
IN1 4
VT0 GND GND VCC
16 15 14 13
NB7VQ58M
5 678
VT1 SEL EQEN VCC
Exposed
Pad (EP)
12 Q
11 GND
10 GND
9Q
MultiLevel Inputs
LVPECL, LVDS, CML
IN0
50 W
VT0
0
50 W
IN0 2:1
IN1 Mux
50 W
VT1
1
50 W
IN1
VCC
SEL 75 kW
EQEN
(Equalizier Enable)
EQ
VCC
GND
75 kW
0
2:1
Mux
1
Figure 1. Pin Configuration (Top View)
Table 1. EQualizer ENable FUNCTION
EQEN
Function
0 INn / INn Inputs Bypass the EQualizer section
1 Inputs flow through the EQualizer
Figure 2. Detailed Block Diagram
Table 2. SELect FUNCTION TRUTH TABLE
SEL Q
Q
L D0
D0
H D1
D1
Q
Q
Table 3. PIN DESCRIPTION
Pin Name
I/O
Description
1 IN0 LVPECL, CML, LVDS Input Noninverted Differential Input (Note 1)
2 IN0 LVPECL, CML, LVDS Input Inverted Differential Input (Note 1)
3 IN1 LVPECL, CML, LVDS Input Noninverted Differential Input (Note 1)
4 IN1 LVPECL, CML, LVDS Input Inverted Differential Input (Note 1)
5 VT1
Internal 50 W Termination Pin for IN1/IN1
6 SEL
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7 EQEN
LVTTL/LVCMOS Input
LVCMOS Input
SEL Input. Low for IN0 inputs, High for IN1 inputs. (Note 1) Pin will default HIGH when
left open (has internal pullup resistor)
Equalizer Enable Input; pin will default LOW when left open (has internal pulldown
resistor)
8 VCC
Positive Supply Voltage (Note 2)
9Q
CML Output
Inverted Differential Output
10 GND
Negative Supply Voltage
11 GND
Negative Supply Voltage
12 Q
CML Output
Noninverted Differential Output
13 VCC
Positive Supply Voltage (Note 2)
14 GND
Negative Supply Voltage
15 GND
Negative Supply Voltage
16 VT0
Internal 50 W Termination Pin for IN0/IN0
EP
The Exposed Pad (EP) on the QFN16 package bottom is thermally connected to the die
for improved heat transfer out of package. The exposed pad must be attached to a
heatsinking conduit. The pad is electrically connected to the die, and must be
electrically and thermally connected to GND on the PC board.
1. In the differential configuration when the input termination pins (VT0, VT1) are connected to a common termination voltage or left open, and
if no signal is applied on IN0/IN0, IN1/IN1 inputs, then the device will be susceptible to selfoscillation. Q/Q outputs have internal 50 W source
termination resistors.
2. All VCC and GND pins must be externally connected to a power supply for proper operation.
http://onsemi.com
2


Part Number NB7VQ58M
Description 1.8V / 2.5V / 3.3V Differential 2:1 Clock/Data Multiplexer / Translator
Maker ON Semiconductor
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