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  ON Semiconductor Electronic Components Datasheet  

NB7V58M Datasheet

1.8 V / 2.5 V / 3.3 V Differential 2:1 Clock / Data Multiplexer / Translator

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NB7V58M
1.8 V / 2.5 V / 3.3 V
Differential 2:1 Clock / Data
Multiplexer / Translator
with CML Outputs
MultiLevel Inputs w/ Internal
Termination
Description
The NB7V58M is a high performance differential 2to1 Clock or
Data multiplexer. The differential inputs incorporate internal 50 W
termination resistors that are accessed through the VT pin. This
feature allows the NB7V58M to accept various logic level standards,
such as LVPECL, CML or LVDS.
The NB7V58M produces minimal Clock or Data jitter operating up
to 7 GHz or 10.7 Gb/s, respectively. As such, the NB7V58M is ideal
for SONET, GigE, Fiber Channel, Backplane and other Clock/Data
distribution applications.
The 16 mA differential CML outputs provide matching internal
50 W terminations and 400 mV output swings when externally
terminated with a 50 W resistor to VCC.
The NB7V58M is offered in a low profile 3 mm x 3 mm 16pin
QFN package and is a member of the GigaCommt family of high
performance Clock / Data products. For applications that require
equalization, the pincompatible NB7VQ58M is also available.
Application notes, models, and support documentation are available at
www.onsemi.com.
Features
www.DataSMheaext4iUm.cuommInput Data Rate > 10.7 Gb/s
Data Dependent Jitter < 10 ps
Maximum Input Clock Frequency > 7 GHz
Random Clock Jitter < 0.8 ps RMS
180 ps Typical Propagation Delay
35 ps Typical Rise and Fall Times
Differential CML Outputs, 400 mV PeaktoPeak, Typical
Operating Range: VCC = 1.71 V to 3.6 V with GND = 0 V
Internal 50 W Input Termination Resistors
QFN16 Package, 3 mm x 3 mm
40°C to +85°C Ambient Operating Temperature
This is a PbFree Device
http://onsemi.com
1
QFN16
MN SUFFIX
CASE 485G
MARKING
DIAGRAM*
16
1
NB7V
58M
ALYW G
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbFree Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
SIMPLIFIED BLOCK DIAGRAM
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
August, 2009 Rev. 0
1
Publication Order Number:
NB7V58M/D


  ON Semiconductor Electronic Components Datasheet  

NB7V58M Datasheet

1.8 V / 2.5 V / 3.3 V Differential 2:1 Clock / Data Multiplexer / Translator

No Preview Available !

NB7V58M
VT0 GND GND VCC
16 15 14 13
Exposed
Pad (EP)
IN0 1
IN0 2
IN1 3
IN1 4
NB7V58M
12 Q
11 GND
10 GND
9Q
5 678
VT1 SEL NC VCC
Figure 1. Pin Configuration (Top View)
MultiLevel Inputs
LVPECL, LVDS, CML
IN0
50 W
VT0
50 W
IN0
IN1
50 W
VT1
50 W
IN1
0
VCC
2:1
Mux
1
25 kW
SEL
Figure 2. Detailed Block Diagram
Q
Q
Table 1. SELect FUNCTION TRUTH TABLE
SEL Q
Q
L IN0 IN0
H IN1 IN1
Table 2. PIN DESCRIPTION
Pin Name
I/O
Description
1 IN0 LVPECL, CML, LVDS Input Noninverted Differential Input (Note 1)
2 IN0 LVPECL, CML, LVDS Input Inverted Differential Input (Note 1)
3 IN1 LVPECL, CML, LVDS Input Noninverted Differential Input (Note 1)
4 IN1 LVPECL, CML, LVDS Input Inverted Differential Input (Note 1)
5 VT1
Internal 50 W Termination Pin for IN1/IN1
6 SEL
www.DataSheet4U.com
7 NC
LVTTL/LVCMOS Input
SEL Input. Low for IN0 inputs, high for IN1 inputs. (Note 1) Pin will default HIGH when
left open
(has internal pullup resistor)
No Connect
8 VCC
Positive Supply Voltage (Note 2)
9Q
CML Output
Inverted Differential Output
10 GND
Negative Supply Voltage
11 GND
Negative Supply Voltage
12 Q
CML Output
Noninverted Differential Output
13 VCC
Positive Supply Voltage (Note 2)
14 GND
Negative Supply Voltage
15 GND
Negative Supply Voltage
16 VT0
Internal 50 W Termination Pin for IN0/IN0
EP
The Exposed Pad (EP) on the QFN16 package bottom is thermally connected to the
die for improved heat transfer out of package. The exposed pad must be attached to
a heatsinking conduit. The pad is electrically connected to the die, and must be elec-
trically and thermally connected to GND on the PC board.
1. In the differential configuration when the input termination pins (VT0, VT1) are connected to a common termination voltage or left open, and
if no signal is applied on IN0/IN0, IN1/IN1 inputs, then the device will be susceptible to selfoscillation. Q/Q outputs have internal 50 W source
termination resistors.
2. All VCC and GND pins must be externally connected to a power supply for proper operation.
http://onsemi.com
2


Part Number NB7V58M
Description 1.8 V / 2.5 V / 3.3 V Differential 2:1 Clock / Data Multiplexer / Translator
Maker ON Semiconductor
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