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NB7V586M Datasheet

1.8V Differential 2:1 Mux Input to 1.2V/1.8V 1:6 CML Clock/Data Fanout Buffer / Translator

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NB7V586M
1.8V Differential 2:1 Mux
Input to 1.2V/1.8V 1:6 CML
Clock/Data Fanout Buffer /
Translator
MultiLevel Inputs w/ Internal Termination
Description
The NB7V586M is a differential 1to6 CML Clock/Data
Distribution chip featuring a 2:1 Clock/Data input multiplexer with an
input select pin. The INx/INx inputs incorporate internal 50 W
termination resistors and will accept differential LVPECL, CML, or
LVDS logic levels (see Figure 12). The INx/INx inputs and core logic
are powered with a 1.8 V supply. The NB7V586M produces six
identical differential CML output copies of Clock or Data. The outputs
are configured as three banks of two differential pair. Each bank (or all
three banks) have the flexibility of being powered by any combination
of either a 1.8 V or 1.2 V supply.
The 16 mA differential CML output structure provides matching
internal 50 W source terminations and 400 mV output swings when
externally terminated with a 50 W resistor to VCCOx (see Figure 11).
The 1:6 fanout design was optimized for low output skew and
minimal jitter and is ideal for SONET, GigE, Fiber Channel,
Backplane and other Clock/Data distribution applications operating
up to 6 GHz or 10 Gb/s typical. The VREFAC reference outputs can be
used to rebias capacitorcoupled differential or singleended input
signals.
The NB7V586M is offered in a low profile 5x5 mm 32pin PbFree
QFN package. Application notes, models, and support documentation
are available at www.onsemi.com.
The NB7V586M is a member of the GigaCommfamily of high
www.DatpaeSrhfeoertm4Uan.ccoemclock products.
Features
Maximum Input Data Rate > 10 Gb/s Typical
Data Dependent Jitter < 10 ps
Maximum Input Clock Frequency > 6 GHz Typical
Random Clock Jitter < 0.8 ps RMS, Max
Low Skew 1:6 CML Outputs, 20 ps Max
2:1 MultiLevel Mux Inputs
175 ps Typical Propagation Delay
50 ps Typical Rise and Fall Times
Differential CML Outputs, 330 mV PeaktoPeak, Typical
Operating Range: VCC = 1.71 V to 1.89 V
Operating Range: VCCOx = 1.14 V to 1.89 V
Internal 50 W Input Termination Resistors
VREFAC Reference Output
QFN32 Package, 5 mm x 5 mm
40°C to +85°C Ambient Operating Temperature
These are PbFree Devices
http://onsemi.com
MARKING
DIAGRAM*
1 32
1
QFN32
MN SUFFIX
CASE 488AM
NB7V
586M
AWLYYWW
G
A
WL
YY
WW
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= PbFree Package
*For additional marking information, refer to
Application Note AND8002/D.
SIMPLIFIED LOGIC DIAGRAM
VCC
SEL
VREFAC0
IN0
VT0
IN0
IN1
VT1
IN1
VREFAC1
VCC
GND
0
1
Q0
Q0
VCCO1
Q1
Q1
Q2
Q2
VCCO2
Q3
Q3
Q4
Q4
VCCO3
Q5
Q5
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
© Semiconductor Components Industries, LLC, 2008
September, 2008 Rev. 0
1
Publication Order Number:
NB7V586M/D


  ON Semiconductor Electronic Components Datasheet  

NB7V586M Datasheet

1.8V Differential 2:1 Mux Input to 1.2V/1.8V 1:6 CML Clock/Data Fanout Buffer / Translator

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NB7V586M
Exposed Pad
(EP)
32 31 30 29 28 27 26 25
IN0 1
24 GND
VT0 2
23 VCC02
VREFAC0 3
22 Q2
IN0 4
IN1 5
NB7V586M
21 Q2
20 Q3
VT1 6
19 Q3
VREFAC1 7
18 VCC02
IN1 8
17
GND
9 10 11 12 13 14 15 16
Table 1. INPUT SELECT FUNCTION TABLE
SEL*
CLK Input Selected
0 IN0
1 IN1
*Defaults HIGH when left open.
Figure 1. 32Lead QFN Pinout (Top View)
Table 2. PIN DESCRIPTION
Pin Name
I/O
Description
1,4 IN0, IN0 LVPECL, CML, Noninverted, Inverted, Differential Inputs
5,8
IN1, IN1
LVDS Input
2,6 VT0, VT1
Internal 100 Ω Centertapped Termination Pin for IN0/IN0 and IN1/IN1
31 SEL LVTTL/LVCMOS Input Select pin; LOW for IN0 Inputs, HIGH for IN1 Inputs; defaults HIGH when left open
Input
10 NC
No Connect
30 VCC
1.8 V Positive Supply Voltage for the Inputs and Core Logic.
25 VCCO1
1.2 V or 1.8 V Positive Supply Voltage for the Q0, Q0, Q1, Q1 CML Outputs
18, 23
VCCO2
1.2 V or 1.8 V Positive Supply Voltage for the Q2, Q2, Q3, Q3 CML Outputs
11, 16
VCCO3
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29, 28
Q0, Q0
27, 26
Q1, Q1
1.2 V or 1.8 V
CML Output
1.2 V or 1.8 V Positive Supply Voltage for the Q4, Q4, Q5, Q5 CML Outputs
Noninverted, Inverted Differential Outputs; powered by VCCO1 (Notes 1 and 2).
22, 21
20, 19
Q2, Q2
Q3, Q3
1.2 V or 1.8 V
CML Output
Noninverted, Inverted Differential Outputs; powered by VCCO2 (Notes 1 and 2).
15, 14
13, 12
Q4, Q4
Q5, Q5
1.2 V or 1.8 V
CML Output
Noninverted, Inverted Differential Outputs; powered by VCCO3 (Notes 1 and 2).
9, 17,
24, 32
GND
Negative Supply Voltage, connected to Ground
3 VREFAC0 Output Voltage Reference for CapacitorCoupled Inputs, only
7 VREFAC1
EP
The Exposed Pad (EP) on the QFN32 package bottom is thermally connected to the
die for improved heat transfer out of package. The exposed pad must be attached to a
heatsinking conduit. The pad is electrically connected to the die, and must be electric-
ally and thermally connected to GND on the PC board.
1. In the differential configuration when the input termination pins (VT0, VT1) are connected to a common termination voltage or left open, and
if no signal is applied on INn/INn input, then, the device will be susceptible to selfoscillation. Qn/Qn outputs have internal 50 W source
termination resistors.
2. All VCC, VCC0x and GND pins must be externally connected to a power supply for proper operation.
http://onsemi.com
2


Part Number NB7V586M
Description 1.8V Differential 2:1 Mux Input to 1.2V/1.8V 1:6 CML Clock/Data Fanout Buffer / Translator
Maker ON Semiconductor
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