NB7V585M Description
Multi−Level Inputs w/ Internal Termination The NB7V585M is a differential 1 −to −6 CML clock/data distribution chip featuring a 2:1 Clock/Data input multiplexer with an input select pin. The INx/INx inputs incorporate internal 50 W termination resistors and will accept LVPECL, CML, or LVDS logic levels (see Figure 9). The NB7V585M produces six identical output copies of clock or data operating up to 6 GHz or 10...
NB7V585M Key Features
- Rev. 1
- CML Outpu
NB7V585M Applications
- For additional marking information, refer to Application Note AND8002/D