SIMPLIFIED LOGIC DIAGRAM VCC Q0 Q0 SEL VREFAC0 IN0 VT0 IN0 0 Q1 Q1 Q2 Q2 IN1 VT1 IN1 VREFAC1 VCC GND 1 Q3 Q3 Q4 Q4 Q5 Q5 ORDERING INFORMATION See detailed orderi.

The 16 mA differential CML output structure provides matching internal 50 W source terminations, 400 mV output swings w.

Multi−Level Inputs w/ Internal Termination The NB7V585M is a differential 1 −to −6 CML clock/data distribution chip featuring a 2:1 Clock/Data input multiplexer with an input select pin. The INx/INx inputs incorporate internal 50 W termination resis.

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