NB7L11M Datasheet | onsemi

NB7L11M 2.5V/3.3V Differential 1:2 Clock/Data Fanout Buffer/ Translator with CML Outputs and Internal Termination Description http://onsemi. MARKING DIAGRAM- 16 1 The NB7L11M is a differential 1- to- 2 clock/data distribution chip with internal source termination and CML output structure, optimized for low skew and minimal jitter. The device is functionally equivalent to the EP11, LVEP11, or SG11 devices. Device produces two identical output copies of clock or data operating up to 8 GHz or 12 Gb/s, respectively. As such, NB7L11M is ideal for SONET, Gig E, Fiber Channel, Backplane and other clock/data distribution applications. Inputs incorporate internal 50 W termination resistors and accept LVPECL, CML, LVCMOS, LVTTL, or LVDS (See Table 6). Differential 16 m A CML output provides matching internal 50 W terminations, and 400 m V output swings when externally terminated, 50 W to VCC (See Figure 14). The device is offered in a low profile 3x3 mm 16- pin QFN package. Application notes, models, and support documentation are available at .onsemi.. Features QFN- 16 MN SUFFIX CASE 485G NB7L 11M ALYWG G A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb- Free Package (Note: Microdot may be in either location) - For additional marking information, refer to Application Note AND8002/D. - Maximum Input Clock Frequency up to 8 GHz Typical - Maximum Input Data Rate up to 12 Gb/s Typical - < 0.5 ps of RMS Clock Jitter - < 10 ps of Data Dependent Jitter - 30 ps Typical Rise and Fall Times .. - 110 ps Typical Propagation Delay - 3 ps Typical Within Device Skew - Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V - CML Output Level (400 m V Peak- to- Peak Output) Differential - - - ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. Output Only 50 W Internal Input and Output Termination Resistors Functionally patible with Existing 2.5 V/3.3 V LVEL, LVEP,...