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  ON Semiconductor Electronic Components Datasheet  

NB7L11M Datasheet

2.5V/3.3V Differential 1:2 Clock/Data Fanout Buffer/ Translator

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NB7L11M
2.5V/3.3V Differential 1:2
Clock/Data Fanout Buffer/
Translator with CML
Outputs and Internal
Termination
Description
The NB7L11M is a differential 1to2 clock/data distribution chip
with internal source termination and CML output structure, optimized
for low skew and minimal jitter. The device is functionally equivalent to
the EP11, LVEP11, or SG11 devices. Device produces two identical
output copies of clock or data operating up to 8 GHz or 12 Gb/s,
respectively. As such, NB7L11M is ideal for SONET, GigE, Fiber
Channel, Backplane and other clock/data distribution applications.
Inputs incorporate internal 50 W termination resistors and accept
LVPECL, CML, LVCMOS, LVTTL, or LVDS (See Table 6).
Differential 16 mA CML output provides matching internal 50 W
terminations, and 400 mV output swings when externally terminated,
50 W to VCC (See Figure 14).
The device is offered in a low profile 3x3 mm 16pin QFN package.
Application notes, models, and support documentation are available at
www.onsemi.com.
Features
Maximum Input Clock Frequency up to 8 GHz Typical
Maximum Input Data Rate up to 12 Gb/s Typical
< 0.5 ps of RMS Clock Jitter
< 10 ps of Data Dependent Jitter
30 ps Typical Rise and Fall Times
www.DataS1h1ee0t4pUs.cToympical Propagation Delay
3 ps Typical Within Device Skew
Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V
CML Output Level (400 mV PeaktoPeak Output) Differential
Output Only
50 W Internal Input and Output Termination Resistors
Functionally Compatible with Existing 2.5 V/3.3 V LVEL, LVEP, EP
and SG Devices
PbFree Packages are Available*
http://onsemi.com
QFN16
MN SUFFIX
CASE 485G
MARKING
DIAGRAM*
16
1
NB7L
11M
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbFree Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
*For additional information on our PbFree strategy and
soldering details, please download the ON Semicon-
ductor Soldering and Mounting Techniques Reference
Manual, SOLDERRM/D.
VTCLK
CLK
CLK
VTCLK
50 W
50 W
Figure 1. Logic Diagram
Q0
Q0
Q1
Q1
© Semiconductor Components Industries, LLC, 2006
January, 2006 Rev. 1
1
Publication Order Number:
NB7L11M/D


  ON Semiconductor Electronic Components Datasheet  

NB7L11M Datasheet

2.5V/3.3V Differential 1:2 Clock/Data Fanout Buffer/ Translator

No Preview Available !

NB7L11M
VCC Q0
16 15
Q0 VCC
14 13
Exposed Pad (EP)
VTCLK 1
CLK 2
CLK 3
VTCLK 4
NB7L11M
12 VEE
11 VEE
10 VEE
9 VEE
5678
VCC Q1 Q1 VCC
Figure 2. QFN16 Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin Name
I/O
Description
1 VTCLK
Internal 50 W Termination Pin for CLK
2 CLK LVPECL, CML, Inverted Differential Clock/Data Input. (Note 1)
LVCMOS, LVTTL,
LVDS
3 CLK LVPECL, CML, Noninverted Differential Clock/Data Input. (Note 1)
LVCMOS, LVTTL,
LVDS
4
5,8,13,16
VTCLK
VCC
Internal 50 W Termination Pin for CLK
Positive Supply Voltage. All VCC pins must be externally connected to a Power Supply
to guarantee proper operation.
6
7
9,10,11,12
Q1
Q1
VEE
CML Output
CML Output
Inverted CLK output 1 with internal 50 W source termination resistor. (Note 2)
Noninverted CLK output 1 with internal 50 W source termination resistor. (Note 2)
Negative Supply Voltage. All VEE pins must be externally connected to a Power Supply
to guarantee proper operation.
www.DataSheet144U.com
15
Q0
Q0
CML Output
CML Output
Inverted CLK output 0 with internal 50 W source termination resistor. (Note 2)
Noninverted CLK output 0 with internal 50 W source termination resistor. (Note 2)
EP
Exposed Pad. The thermally exposed pad on package bottom (see case drawing) must
be attached to a heatsinking conduit. It is recommended to connect the EP to the lower
potential (VEE).
1. In the differential configuration when the input termination pins (VTCLK, VTCLK) are connected to a common termination voltage or left open,
and if no signal is applied on CLK and CLK then the device will be susceptible to selfoscillation.
2. CML outputs require 50 W receiver termination resistor to VCC for proper operation.
http://onsemi.com
2


Part Number NB7L11M
Description 2.5V/3.3V Differential 1:2 Clock/Data Fanout Buffer/ Translator
Maker ON Semiconductor
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NB7L11M Datasheet PDF






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