NB6LQ572 Description
Each INx/INx input pair incorporates a fixed Equalizer Receiver, which when placed in series with a Clock / Data path, will enhance the degraded signal transmitted across an FR4 backplane or cable interconnect. For applications that do not require Equalization, consider the NB6L572, which is pin−patible to the NB6LQ572. The differential Clock / Data inputs have internal 50 W termination resistors and will accept...
NB6LQ572 Key Features
- Rev. 0