MM74HCT541 Datasheet | onsemi

Octal 3-State Buffer, Inverting/Non-Inverting MM74HCT540, MM74HCT541 General Description The MM74HCT540 and MM74HCT541 3- STATE buffers utilize advanced silicon- gate CMOS technology and are general purpose high speed inverting and non- inverting buffers. They possess high drive current outputs which enable high speed operation even when driving large bus capacitances. These circuits achieve speeds parable to low power Schottky devices, while retaining the low power consumption of CMOS. Both devices are TTL input patible and have a fanout of 15 LS- TTL equivalent inputs. MM74HCT devices are intended to interface between TTL and NMOS ponents and standard CMOS devices. These parts are also plug- in replacements for LS- TTL devices and can be used to reduce power consumption in existing designs. The MM74HCT540 is an inverting buffer and the MM74HCT541 is a non- inverting buffer. The 3- STATE control gate operates as a two- input NOR such that if either G1 or G2 are HIGH, all eight outputs are in the high- impedance state. In order to enhance PC board layout, the MM74HCT540 and MM74HCT541 offers a pinout having inputs and outputs on opposite sides of the package. All inputs are protected from damage due to static discharge by diodes to VCC and ground. Features - TTL Input patible - Typical Propagation Delay: 12 ns - 3- STATE Outputs for Connection to System Buses - Low Quiescent Current: 160 m A - Output Current: 6 m A (min) - These are Pb- Free Devices DATA SHEET .onsemi. SOIC- 20 WB TSSOP- 20 WB TSSOP- 20 CASE 751D- 05 CASE 948E CASE 948AQ MARKING DIAGRAMS XXXXXX AWLYYWWG XXX XXX ALYWG G 1 XXXXX = Specific Device Code = Assembly Location L/WL = Wafer Lot = Year YW/WW = Work Week G or G = Pb- Free Package (Note: Microdot may be in either location) CONNECTION DIAGRAMS Pin Assignment for SOIC and TSSOP MM74HCT540 (Top View) © Semiconductor ponents Industries, LLC, 1984 December,...