MC74ACT646 - Octal Transceiver/Register

onsemi

Download the MC74ACT646 datasheet PDF. This datasheet also covers the MC74AC646 variant, as both devices belong to the same octal transceiver/register family and are provided as variant models within a single manufacturer datasheet.

Features

Independent Registers for A and B Buses.
Multiplexed Real.
Time and Stored Data Transfers.
Choice of True and Inverting Data Paths.
3.
State Outputs.
300 mil Slim Dual In.
Line Package.
Outputs Source/Sink 24 mA.
′ACT646 Has TTL Compatible Inputs.
These are Pb.
Free Devices REAL TIME.

📥 Download Datasheet

MC74ACT646 octal transceiver/register by onsemi - Datasheet Preview — Note: The manufacturer provides a single datasheet file (MC74AC646_ONSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number	MC74ACT646
Manufacturer	onsemi
File Size	327.76 KB
Description	Octal Transceiver/Register
Datasheet	MC74ACT646 Datasheet

📁 Similar Datasheet

Part Number	Description	Manufacturer
MC74ACT646	OCTAL TRANSCEIVER/REGISTER	Motorola
MC74ACT640	OCTAL BIDIRECTIONAL TRANSCEIVER	Motorola
MC74ACT643	OCTAL BIDIRECTIONAL TRANSCEIVER	Motorola
MC74ACT648	OCTAL TRANSCEIVER/REGISTER	Motorola
MC74ACT620	OCTAL BIDIRECTIONAL TRANSCEIVER	Motorola

Other Datasheets by onsemi

Part Number	Description
MC74ACT640	Octal 3-State Inverting Transciever
MC74ACT652	Octal Transceiver/Register
MC74ACT00	Quad 2-Input NAND Gate
MC74ACT02	Quad 2-Input NOR Gate
MC74ACT04	Hex Inverter

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text

MC74AC646, MC74ACT646 Octal Transceiver/Register with 3-State Outputs (Non-inverting) The MC74AC646/74ACT646 consist of registered bus transceiver circuits, with outputs, D−type flip−flops and control circuitry providing multiplexed transmission of data directly from the input bus or from the internal storage registers. Data on the A or B bus will be loaded into the respective registers on the LOW−to−HIGH transition of the appropriate clock pin (CAB or CBA). The four fundamental data handling functions available are illustrated Figures 1 to 4.