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  ON Semiconductor Electronic Components Datasheet  

MC14027B Datasheet

Dual J-K Flip-Flop

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MC14027B
Dual J-K Flip-Flop
The MC14027B dual J−K flip−flop has independent J, K, Clock (C),
Set (S) and Reset (R) inputs for each flip−flop. These devices may be
used in control, register, or toggle functions.
Features
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Logic Swing Independent of Fanout
Logic Edge−Clocked Flip−Flop Design
Logic State is Retained Indefinitely with Clock Level Either High or
Low; Information is Transferred to the Output Only on the
Positive−Going Edge of the Clock Pulse
Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
Pin−for−Pin Replacement for CD4027B
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
This Device is Pb−Free and is RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
−0.5 to +18.0
−0.5 to VDD + 0.5
V
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
± 10 mA
PD Power Dissipation, per Package
(Note 1)
500
mW
TA Ambient Temperature Range
−55 to +125
°C
Tstg Storage Temperature Range
−65 to +150
°C
TL Lead Temperature
(8−Second Soldering)
260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
SOIC−16
D SUFFIX
CASE 751B
PIN ASSIGNMENT
QA 1
QA 2
CA 3
RA 4
KA 5
JA 6
SA 7
VSS 8
16 VDD
15 QB
14 QB
13 CB
12 RB
11 KB
10 JB
9 SB
MARKING DIAGRAM
16
14027BG
AWLYWW
1
A
WL
YY, Y
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 8
1
Publication Order Number:
MC14027B/D


  ON Semiconductor Electronic Components Datasheet  

MC14027B Datasheet

Dual J-K Flip-Flop

No Preview Available !

MC14027B
CJ
1
X
0
X
1
X
XX
XX
XX
X = Don’t Care
= Level Change
TRUTH TABLE
Inputs
Outputs*
K
S
R
Qn‡
Qn+1
Qn+1
X000
1
0
0001
1
0
X000
0
1
1001
0
1
1 0 0 Qo Qo Qo
X 0 0 X Qn Qn
X10X
1
0
X01X
0
1
X11X
1
= Present State
* = Next State
1
No
Change
BLOCK DIAGRAM
7
6 J SQ 1
3C
5K
Q2
R
4
9
10 J S Q 15
13 C
11 K
Q 14
R
12
VDD = PIN 16
VSS = PIN 8
ORDERING INFORMATION
Device
Package
Shipping
MC14027BDG
SOIC−16
(Pb−Free)
48 Units / Rail
NLV14027BDG*
SOIC−16
(Pb−Free)
48 Units / Rail
MC14027BDR2G
SOIC−16
(Pb−Free)
2500 Units / Tape & Reel
NLV14027BDR2G*
SOIC−16
(Pb−Free)
2500 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
http://onsemi.com
2


Part Number MC14027B
Description Dual J-K Flip-Flop
Maker ON Semiconductor
Total Page 6 Pages
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