MC100EP196 - 3.3V ECL Programmable Delay Chip

onsemi

General Description

Pin Name I/O Default State Description 23, 25, 26, 27, 29, 30, 31, 32, 1, 2 D[0:9] LVCMOS, LVTTL, ECL Input LOW Single

ended Parallel Data Inputs [0:9].

Internal 75 kW to VEE.

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MC100EP196 3.3v ecl programmable delay chip by onsemi - Datasheet Preview

Datasheet Details

Part number	MC100EP196
Manufacturer	onsemi
File Size	260.80 KB
Description	3.3V ECL Programmable Delay Chip
Datasheet	MC100EP196 Datasheet

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Other Datasheets by onsemi

Part Number	Description
MC100EP196A	3.3 V ECL Programmable Delay Chip
MC100EP196B	3.3 V ECL Programmable Delay Chip
MC100EP195	3.3V ECL Programmable Delay Chip
MC100EP195B	3.3V ECL Programmable Delay Chip
MC100EP101	3.3V / 5V ECL Quad 4-Input OR/NOR

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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3.3 V ECL Programmable Delay Chip with FTUNE MC100EP196 The MC100EP196 is a programmable delay chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar architecture to the EP195 with the added feature of further tuneability in delay using the FTUNE pin. The FTUNE input takes an analog voltage from VCC to VEE to fine tune the output delay from 0 to 60 ps. The delay section consists of a programmable matrix of gates and multiplexers as shown in the logic diagram, Figure 2. The delay increment of the EP196 has a digitally selectable resolution of about 10 ps and a net range of up to 10.2 ns.