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MC100EP195B Datasheet 3.3V ECL Programmable Delay Chip

Manufacturer: onsemi

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Datasheet Details

Part number MC100EP195B
Manufacturer onsemi
File Size 376.43 KB
Description 3.3V ECL Programmable Delay Chip
Datasheet download datasheet MC100EP195B Datasheet

General Description

s The MC100EP195B is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment.

It provides variable delay of a differential NECL/PECL input transition.

The delay section consists of a programmable matrix of gates and multiplexers as shown in the logic diagram, Figure 2.

Overview

3.3 V ECL Programmable Delay Chip MC100EP195B.

Key Features

  • Maximum Input Clock Frequency >1.2 GHz Typical.
  • Programmable Range: 0 ns to 10 ns.
  • Delay Range: 2.2 ns to 12.2 ns.
  • 10 ps Increments.
  • PECL Mode Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V.
  • NECL Mode Operating Range: VCC = 0 V with VEE =.
  • 3.0 V to.
  • 3.6 V.
  • IN/IN Inputs Accept LVPECL, LVNECL, LVDS Levels.
  • A Logic High on the EN Pin Will Force Q to Logic Low.
  • D[10:0] Can Select Either LVPECL, L.

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