MC100EP195B Description
3.3 V ECL Programmable Delay Chip MC100EP195B Descriptions The MC100EP195B is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The delay section consists of a programmable matrix of gates and multiplexers as shown in the logic diagram, Figure.
MC100EP195B Key Features
- Maximum Input Clock Frequency >1.2 GHz