MC100EP195B chip equivalent, 3.3v ecl programmable delay chip.
* Maximum Input Clock Frequency >1.2 GHz Typical
* Programmable Range: 0 ns to 10 ns
* Delay Range: 2.2 ns to 12.2 ns
* 10 ps Increments
* PECL Mode O.
The MC100EP195B is a Programmable Delay Chip (PDC)
designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition.
The delay section consists of a programmable matrix of gates an.
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