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MC100EP195 - 3.3V ECL Programmable Delay Chip

Description

Pin Name I/O Default State Description 23, 25, 26, 27, D[0:9] LVCMOS, LVTTL, Low Single

Ended Parallel Data Inputs [0:9].

Internal 75 kW to VEE.

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Datasheet Details

Part number MC100EP195
Manufacturer onsemi
File Size 303.17 KB
Description 3.3V ECL Programmable Delay Chip
Datasheet download datasheet MC100EP195 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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3.3 V ECL Programmable Delay Chip MC100EP195 The MC100EP195 is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The delay section consists of a programmable matrix of gates and www.onsemi.com multiplexers as shown in the logic diagram, Figure 3. The delay increment of the EP195 has a digitally selectable resolution of about 10 ps and a net range of up to 10.2 ns. The required delay is selected by the 10 data select inputs D[9:0] values and controlled by the LEN (pin 10). A LOW level on LEN allows a transparent LOAD mode of 1 32 real time delay values by D[9:0].
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