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MC100EL30 - Triple D Flip-Flop

Description

differential outputs.

Data enters the master latch when the clock input is LOW and transfers to the slave upon a positive transition on the clock input.

In addition to a common Set input individual Reset inputs are provided for each flip flop.

Features

  • 1200 MHz Minimum Toggle Frequency.
  • 450 ps Typical Propagation Delays.
  • ESD Protection: > 2 kV Human Body Model.
  • The 100 Series Contains Temperature Compensation.
  • PECL Mode Operating Range:.
  • VCC = 4.2 V to 5.7 V with VEE = 0 V.
  • NECL Mode Operating Range:.
  • VCC = 0 V with VEE =.
  • 4.2 V to.
  • 5.7 V.
  • Internal Input 75 kW Pulldown Resistors.
  • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test.

📥 Download Datasheet

Datasheet Details

Part number MC100EL30
Manufacturer onsemi
File Size 130.15 KB
Description Triple D Flip-Flop
Datasheet download datasheet MC100EL30 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
MC100EL30 5 V ECL Triple D Flip-Flop with Set and Reset Description The MC100EL30 is a triple master-slave D flip-flop with differential outputs. Data enters the master latch when the clock input is LOW and transfers to the slave upon a positive transition on the clock input. In addition to a common Set input individual Reset inputs are provided for each flip flop. Both the Set and Reset inputs function asynchronous and overriding with respect to the clock inputs. Features • 1200 MHz Minimum Toggle Frequency • 450 ps Typical Propagation Delays • ESD Protection: > 2 kV Human Body Model • The 100 Series Contains Temperature Compensation. • PECL Mode Operating Range: ♦ VCC = 4.2 V to 5.7 V with VEE = 0 V • NECL Mode Operating Range: ♦ VCC = 0 V with VEE = −4.2 V to −5.
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