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MC100E131 - 4-BIT D FLIP-FLOP

Description

differential outputs.

Each flip-flop may be clocked separately by holding Common Clock (CC) LOW and using the Clock Enable (CE) inputs for clocking.

Features

  • 1100 MHz Min. Toggle Frequency.
  • Differential Outputs.
  • Individual and Common Clocks.
  • Individual Resets (asynchronous).
  • Paired Sets (asynchronous).
  • PECL Mode Operating Range:.
  • VCC = 4.2 V to 5.7 V with VEE = 0 V.
  • NECL Mode Operating Range:.
  • VCC = 0 V with VEE =.
  • 4.2 V to.
  • 5.7 V.
  • Metastability Time Constant is 200 ps.
  • Internal Input 50 kW Pulldown Resistors.
  • ESD Protection:.

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Datasheet Details

Part number MC100E131
Manufacturer onsemi
File Size 145.49 KB
Description 4-BIT D FLIP-FLOP
Datasheet download datasheet MC100E131 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
MC10E131, MC100E131 5 V ECL 4‐Bit D Flip‐Flop Description The MC10E/100E131 is a quad master-slave D-type flip-flop with differential outputs. Each flip-flop may be clocked separately by holding Common Clock (CC) LOW and using the Clock Enable (CE) inputs for clocking. Common clocking is achieved by holding the CE inputs LOW and using CC to clock all four flip-flops. In this case, the CE inputs perform the function of controlling the common clock, to each flip-flop. Individual asynchronous resets are provided (R). Asynchronous set controls (S) are ganged together in pairs, with the pairing chosen to reflect physical chip symmetry. Data enters the master when both CC and CE are LOW, and transfers to the slave when either CC or CE (or both) go HIGH.
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