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P3055LD Datasheet Preview

P3055LD Datasheet

N-Channel Logic Level Enhancement Mode Field Effect Transistor

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NIKO-SEM
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
P3055LD
TO-252 (DPAK)
PRODUCT SUMMARY
V(BR)DSS
RDS(ON)
25 50mΩ
ID
12A
D
G
S
1. GATE
2. DRAIN
3. SOURCE
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted)
PARAMETERS/TEST CONDITIONS
SYMBOL
Gate-Source Voltage
VGS
Continuous Drain Current
Pulsed Drain Current1
TC = 25 °C
TC = 100 °C
ID
IDM
Avalanche Energy
Repetitive Avalanche Energy2
L = 0.1mH
L = 0.05mH
EAS
EAR
Power Dissipation
TC = 25 °C
TC =D1a0ta0S°hCeet4U.com
PD
Operating Junction & Storage Temperature Range
Lead Temperature (1/16” from case for 10 sec.)
Tj, Tstg
TL
LIMITS
±20
12
8
45
60
3
48
20
-55 to 150
275
UNITS
V
A
mJ
W
DataShee
°C
THERMAL RESISTANCE RATINGS
THERMAL RESISTANCE
SYMBOL
Junction-to-Case
RθJC
Junction-to-Ambient
RθJA
Case-to-Heatsink
RθCS
1Pulse width limited by maximum junction temperature.
2Duty cycle 1%
TYPICAL
1
MAXIMUM
3
75
UNITS
°C / W
ELECTRICAL CHARACTERISTICS (TC = 25 °C, Unless Otherwise Noted)
PARAMETER
SYMBOL
TEST CONDITIONS
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
V(BR)DSS
VGS(th)
IGSS
IDSS
STATIC
VGS = 0V, ID = 250µA
VDS = VGS, ID = 250µA
VDS = 0V, VGS = ±20V
VDS = 20V, VGS = 0V
VDS = 20V, VGS = 0V, TJ = 125 °C
LIMITS
MIN TYP MAX
UNIT
25
0.8 1.2 2.5
V
±250 nA
25
µA
250
DataSheet4U.com
DataSheet4 U .com
1 DEC-01-2001




Niko

P3055LD Datasheet Preview

P3055LD Datasheet

N-Channel Logic Level Enhancement Mode Field Effect Transistor

No Preview Available !

www.DataSheet4U.com
NIKO-SEM
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
P3055LD
TO-252 (DPAK)
On-State Drain Current1
Drain-Source On-State
Resistance1
Forward Transconductance1
ID(ON)
RDS(ON)
gfs
VDS = 10V, VGS = 10V
VGS = 5V, ID = 12A
VGS = 10V, ID = 12A
VDS = 15V, ID = 12A
12 A
70 120
mΩ
50 90
16 S
DYNAMIC
Input Capacitance
Ciss
450
Output Capacitance
Coss VGS = 0V, VDS = 15V, f = 1MHz
200 pF
Reverse Transfer Capacitance
Crss
60
Total Gate Charge2
Gate-Source Charge2
Gate-Drain Charge2
Qg
Qgs VDS = 0.5V(BR)DSS, VGS = 10V,
Qgd ID = 6A
15
2.0 nC
7.0
Turn-On Delay Time2
td(on)
6.0
Rise Time2
Turn-Off Delay Time2
tr VDS = 15V, RL = 1Ω
6.0
nS
td(off)
ID 12A, VGS = 10V, RGS = 2.5Ω
20
Fall Time2
tf
5.0
SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C)
et4U.com Continuous Current
IS DataSheet4U.com
Pulsed Current3
ISM
Forward Voltage1
VSD IF = IS, VGS = 0V
Reverse Recovery Time
trr
30
Peak Reverse Recovery Current
IRM(REC)
IF = IS, dlF/dt = 100A / µS
15
Reverse Recovery Charge
Qrr
1Pulse test : Pulse Width 300 µsec, Duty Cycle 2%.
2Independent of operating temperature.
3Pulse width limited by maximum junction temperature.
0.043
12
20
1.5
A
V
nS
A
µC
REMARK: THE PRODUCT MARKED WITH “P3055LD”, DATE CODE or LOT #
DataShee
DataSheet4U.com
DataSheet4 U .com
2 DEC-01-2001


Part Number P3055LD
Description N-Channel Logic Level Enhancement Mode Field Effect Transistor
Maker Niko
Total Page 4 Pages
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