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Niko-Sem

P45N02LD Datasheet Preview

P45N02LD Datasheet

N-Channel Logic Level Enhancement Mode Field Effect Transistor

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NIKO-SEM
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
P45N02LD
TO-252 (DPAK)
PRODUCT SUMMARY
V(BR)DSS
RDS(ON)
25 20mΩ
ID
45A
D
G
S
1. GATE
2. DRAIN
3. SOURCE
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted)
PARAMETERS/TEST CONDITIONS
SYMBOL
Gate-Source Voltage
Continuous Drain Current
Pulsed Drain Current1
TC = 25 °C
TC = 100 °C
Avalanche Current
Avalanche Energy
Repetitive Avalanche Energy2
L = 0.1mH
L = 0.05mH
Power Dissipation
TC = 25 °C
TC = 100 °C
Operating Junction & Storage Temperature Range
Lead Temperature (1/16” from case for 10 sec.)
VGS
ID
IDM
IAR
EAS
EAR
PD
Tj, Tstg
TL
LIMITS
±20
45
28
140
20
140
5.6
55
33
-55 to 150
275
UNITS
V
A
mJ
W
°C
THERMAL RESISTANCE RATINGS
THERMAL RESISTANCE
SYMBOL
Junction-to-Case
RθJC
Junction-to-Ambient
RθJA
Case-to-Heatsink
RθCS
1Pulse width limited by maximum junction temperature.
2Duty cycle 1
TYPICAL
0.7
MAXIMUM
3
70
UNITS
°C / W
ELECTRICAL CHARACTERISTICS (TC = 25 °C, Unless Otherwise Noted)
PARAMETER
SYMBOL
TEST CONDITIONS
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Current1
V(BR)DSS
VGS(th)
IGSS
IDSS
ID(ON)
STATIC
VGS = 0V, ID = 250µA
VDS = VGS, ID = 250µA
VDS = 0V, VGS = ±20V
VDS = 20V, VGS = 0V
VDS = 20V, VGS = 0V, TJ = 125 °C
VDS = 10V, VGS = 10V
LIMITS
UNIT
MIN TYP MAX
25
0.8 1.2
2.5
V
±250 nA
25
µA
250
45 A
1 MAY-24-2001
Free Datasheet http://www.datasheet4u.com/




Niko-Sem

P45N02LD Datasheet Preview

P45N02LD Datasheet

N-Channel Logic Level Enhancement Mode Field Effect Transistor

No Preview Available !

NIKO-SEM
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
Drain-Source On-State
Resistance1
Forward Transconductance1
RDS(ON)
gfs
VGS = 7V, ID = 18A
VGS = 10V, ID = 20A
VDS = 15V, ID = 30A
DYNAMIC
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge2
Gate-Source Charge2
Gate-Drain Charge2
Turn-On Delay Time2
Rise Time2
Turn-Off Delay Time2
Fall Time2
Ciss
Coss
Crss
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
VGS = 0V, VDS = 15V, f = 1MHz
VDS = 0.5V(BR)DSS, VGS = 10V,
ID = 20A
VDS = 15V, RL = 1Ω
ID 30A, VGS = 10V, RGS = 2.5Ω
SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C)
Continuous Current
Pulsed Current3
Forward Voltage1
IS
ISM
VSD IF = IS, VGS = 0V
Reverse Recovery Time
trr
Peak Reverse Recovery Current
IRM(REC)
IF = IS, dlF/dt = 100A / µS
Reverse Recovery Charge
Qrr
1Pulse test : Pulse Width 300 µsec, Duty Cycle 2.
2Independent of operating temperature.
3Pulse width limited by maximum junction temperature.
REMARK: THE PRODUCT MARKED WITH “P45N02LD”, DATE CODE or LOT #
P45N02LD
TO-252 (DPAK)
20 30
mΩ
15 28
16 S
600
290 pF
100
25
2.9 nC
7.0
7.0
7.0
nS
24
6.0
45
150
1.3
37
200
0.043
A
V
nS
A
µC
2 MAY-24-2001
Free Datasheet http://www.datasheet4u.com/


Part Number P45N02LD
Description N-Channel Logic Level Enhancement Mode Field Effect Transistor
Maker Niko-Sem
Total Page 3 Pages
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