SCANPSC110F Datasheet | National Semiconductor

Description The SCANPSC110F Bridge extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a hierarchical approach over a single serial scan chain is improved test throughput and the ability to remove a board from the system and retain test access to the remaining modules. Each SCANPSC110F Bridge supports up to 3 local scan rings which can be accessed individually or bined serially. Addressing is acplished by loading the instruction register with a value matching that of the Slot inputs. Backplane and inter-board testing can easily be acplished by parking the local TAP Controllers in one of the stable TAP Controller states via a Park instruction. The 32-bit TCK counter enables built in self test operations to be performed on one port while other scan chains are simultaneously tested. n The 6 slot inputs support up to 59 unique addresses, a Broadcast Address, and 4 Multi-cast Group Addresses n 3 IEEE 1149.1-patible configurable local scan ports n Mode Register allows local TAPs to be bypassed, selected for insertion into the scan chain individually, or serially in groups of two or three n 32-bit TCK counter n 16-bit LFSR Signature pactor n Local TAPs can be tri-stated via the OE input to allow an alternate test master to take control of the local TAPs n The IP version of this device supports features not described in this datasheet such as 8 slot inputs for enhanced address capability and additional instructions. For a pleted description of the additional instructions supported, refer to the SCANPSC110 supplemental datasheet. Features n True IEEE1149.1 hierarchical and multidrop addressable capability Connection Diagrams 28-Pin CDIP and Flatpak Pin Assignment for LCC DS100327-2 DS100327-1 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1999 National Semiconductor Corporation DS100327 .national. Connection Diagrams Order Number SCANPSC110FFMQB SCANPSC110FDMQB SCANPSC110FLMQB (C...