s A new, high performance, on-chip Floppy Disk
Controller (FDC) provides:
— Software compatibility with the PC8477, which
contains a superset of the floppy disk controller
functions in the µDP8473, the NEC µPD765A
and the N82077
— A modifiable 13-bit address
— Ten IRQ channel options
— Four 8-bit DMA channel options
— 16-byte FIFO
— Burst and non-burst modes
— Low-power CMOS with enhanced power-down
mode
— A new, high-performance, on-chip, digital data
separator without external filter components
— Support for 5.25"/3.5" floppy disk drives
— Automatic media sense support
— Perpendicular recording drive support
— Three mode Floppy Disk Drive (FDD) support
— Full support for IBM’s Tape Drive Register
(TDR) implementation
— Support for new fast tape drives (2 Mbps) and
standard tape drives (1 Mbps, 500 Kbps and
250 Kbps)
— Support for both FM and MFM modes.
s Two Serial Communication Controllers provide:
— Software compatibility with the 16550A and the
16450
— A modifiable 13-bit address
— Ten IRQ channel options
— MIDI baud rate support
— Four 8-bit DMA channel options on SCC2
— Shadow register support UART write-only bits
s A fast universal Infrared interface on SCC2 sup-
ports the following:
— Data rates of up to 115.2 Kbps (SIR)
— A data rate of 1.152 Mbps (MIR)
— A data rate of 4.0 Mbps (FIR)
— Selectable internal or external modulation/de-
modulation (Sharp-IR)
— Consumer Electronic IR mode
s A bidirectional parallel port that includes:
— A modifiable 13-bit address
— Ten IRQ channel options
— Four 8-bit DMA channel options
— An Enhanced Parallel Port (EPP) compatible
with version EPP 1.9 (IEEE1284 compliant),
that also supports version EPP 1.7 of the Xir-
com specification.
— An Extended Capabilities Port (ECP) that is
IEEE1284 compliant, including level 2
— Bidirectional data transfer under either soft-
ware or hardware control
— Compatibility with ISA, EISA, and MicroChan-
nel parallel ports
— Multiplexing of additional external FDC signals
on parallel port pins that enables use of an ex-
ternal Floppy Disk Drive (FDD)
— A protection circuit that prevents damage to the
parallel port when an external printer powers
up or operates at high voltages
— 14 mA output drivers
s Two general purpose pins for two programmable
chip select signals can be programmed for game
port control.
s An address decoder that:
— Selects all primary and secondary ISA ad-
dresses, including COM1-4 and LPT1-3
— Decodes up to 16 address bits
s Clock source:
— An internal clock multiplier generates all re-
quired internal frequencies.
— A clock input source 14.318 MHz, 24 MHz, or
48 MHz may be selected
s Enhanced power management features:
— Special power-down configuration registers
— Enhanced programmable FDC command to
trigger power down
— Programmable power-down and wake-up
modes
— Two dedicated pins for FDC power manage-
ment
— Low power-down current consumption (typical-
ly for PC97338, 400 µA for 3.3V and 600 µA for
5V application)
— Reduced pin leakage current
— Low power CMOS technology
— The ability to shut off clocks to either the entire
chip or only to specific modules
s Mixed voltage support provides:
— Standard 5 V operation
— Low voltage 3.3 V operation
— Simultaneous internal 3.3 V operation and re-
ception or transmission to devices that have ei-
ther 3.3 V or 5 V power supply
s 100-pin TQFP VJG package - PC87338/PC97338
s 100-pin PQFP VLJ package - PC87338/PC97338
2 www.national.com
