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NM24C05 - Serial EEPROM

Download the NM24C05 datasheet PDF. This datasheet also covers the NM24C03 variant, as both devices belong to the same serial eeprom family and are provided as variant models within a single manufacturer datasheet.

Description

The NM24C03 C05 C09 C17 devices are 2048 4096 8192 16 834 bits respectively of CMOS non-volatile electrically erasable memory These devices conform to all specifications in the I2C 2-wire protocol and are designed to minimize device pin count and simplify PC board layout requirements The upper half

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Note: The manufacturer provides a single datasheet file (NM24C03-NationalSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
NM24C05 4K-Bit Standard 2-Wire Bus Interface Serial EEPROM Fairchild
NM24C02 2K-Bit Standard 2-Wire Bus Fairchild
NM24C03 2K-Bit Standard 2-Wire Bus Fairchild
NM24C04 4K-Bit Standard 2-Wire Bus Interface Serial EEPROM Fairchild
NM24C08 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM Fairchild

Other Datasheets by National Semiconductor (Texas Instruments)

Part Number Description
NM24C03 Serial EEPROM
NM24C17 Serial EEPROM
NM27C512 High Performance CMOS EPROM
NM29A040 (NM29A040 / NM29A080) 4-Mbit/8-Mbit CMOS Serial FLASH E2PROM
NM29A080 (NM29A040 / NM29A080) 4-Mbit/8-Mbit CMOS Serial FLASH E2PROM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
NM24C03 C05 C09 C17 2K- 4K- 8K- 16K-Bit Serial EEPROM with Write Protect (I2C Synchronous 2-Wire Bus) January 1993 NM24C03 C05 C09 C17 2K- 4K- 8K- 16K-Bit Serial EEPROM with Write Protect (I2C Synchronous 2-Wire Bus) General Description The NM24C03 C05 C09 C17 devices are 2048 4096 8192 16 834 bits respectively of CMOS non-volatile electrically erasable memory These devices conform to all specifications in the I2C 2-wire protocol and are designed to minimize device pin count and simplify PC board layout requirements The upper half of the memory can be disabled (Write Protected) by connecting the WP pin to VCC This section of memory then becomes unalterable unless WP is switched to VSS This communication protocol uses CLOCK (SCL) and DATA I O (SDA) lines to synchronously clock data betwe