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National Semiconductor Electronic Components Datasheet

LF298 Datasheet

Monolithic Sample-and-Hold Circuits

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July 2000
LF198/LF298/LF398, LF198A/LF398A
Monolithic Sample-and-Hold Circuits
General Description
The LF198/LF298/LF398 are monolithic sample-and-hold
circuits which utilize BI-FET technology to obtain ultra-high
dc accuracy with fast acquisition of signal and low droop
rate. Operating as a unity gain follower, dc gain accuracy is
0.002% typical and acquisition time is as low as 6 µs to
0.01%. A bipolar input stage is used to achieve low offset
voltage and wide bandwidth. Input offset adjust is accom-
plished with a single pin, and does not degrade input offset
drift. The wide bandwidth allows the LF198 to be included in-
side the feedback loop of 1 MHz op amps without having sta-
bility problems. Input impedance of 1010allows high
source impedances to be used without degrading accuracy.
P-channel junction FET’s are combined with bipolar devices
in the output amplifier to give droop rates as low as 5 mV/min
with a 1 µF hold capacitor. The JFET’s have much lower
noise than MOS devices used in previous designs and do
not exhibit high temperature instabilities. The overall design
guarantees no feed-through from input to output in the hold
mode, even for input signals equal to the supply voltages.
Features
n Operates from ±5V to ±18V supplies
n Less than 10 µs acquisition time
n TTL, PMOS, CMOS compatible logic input
n 0.5 mV typical hold step at Ch = 0.01 µF
n Low input offset
n 0.002% gain accuracy
n Low output noise in hold mode
n Input characteristics do not change during hold mode
n High supply rejection ratio in sample or hold
n Wide bandwidth
n Space qualified, JM38510
Logic inputs on the LF198 are fully differential with low input
current, allowing direct connection to TTL, PMOS, and
CMOS. Differential threshold is 1.4V. The LF198 will operate
from ±5V to ±18V supplies.
An “A” version is available with tightened electrical
specifications.
Typical Connection and Performance Curve
Acquisition Time
DS005692-32
Functional Diagram
DS005692-16
© 2000 National Semiconductor Corporation DS005692
DS005692-1
www.national.com
This datasheet has been downloaded from http://www.digchip.com at this page


National Semiconductor Electronic Components Datasheet

LF298 Datasheet

Monolithic Sample-and-Hold Circuits

No Preview Available !

Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
±18V
Power Dissipation (Package
Limitation) (Note 2)
500 mW
Operating Ambient Temperature Range
LF198/LF198A
−55˚C to +125˚C
LF298
−25˚C to +85˚C
LF398/LF398A
0˚C to +70˚C
Storage Temperature Range
−65˚C to +150˚C
Input Voltage
Equal to Supply Voltage
Logic To Logic Reference
Differential Voltage (Note 3)
+7V, −30V
Output Short Circuit Duration
Indefinite
Hold Capacitor Short
Circuit Duration
Lead Temperature (Note 4)
H package (Soldering, 10 sec.)
N package (Soldering, 10 sec.)
M package:
Vapor Phase (60 sec.)
Infrared (15 sec.)
Thermal Resistance (θJA) (typicals)
H package 215˚C/W (Board mount in still air)
85˚C/W (Board mount in
400LF/min air flow)
N package 115˚C/W
M package 106˚C/W
θJC (H package, typical) 20˚C/W
10 sec
260˚C
260˚C
215˚C
220˚C
Electrical Characteristics
The following specifcations apply for −VS + 3.5V VIN +VS − 3.5V, +VS = +15V, −VS = −15V, TA = Tj = 25˚C, Ch = 0.01 µF,
RL = 10 k, LOGIC REFERENCE = 0V, LOGIC HIGH = 2.5V, LOGIC LOW = 0V unless otherwise specified.
Parameter
Conditions
LF198/LF298
LF398
Units
Min Typ Max Min Typ Max
Input Offset Voltage, (Note 5)
Tj = 25˚C
Full Temperature Range
13
5
2 7 mV
10 mV
Input Bias Current, (Note 5)
Tj = 25˚C
Full Temperature Range
5 25
75
10 50 nA
100 nA
Input Impedance
Gain Error
Tj = 25˚C
Tj = 25˚C, RL = 10k
Full Temperature Range
1010
0.002
0.005
0.02
1010
0.004
0.01
0.02
%
%
Feedthrough Attenuation Ratio
at 1 kHz
Tj = 25˚C, Ch = 0.01 µF
86 96
80 90
dB
Output Impedance
Tj = 25˚C, “HOLD” mode
Full Temperature Range
0.5 2
4
0.5 4
6
“HOLD” Step, (Note 6)
Supply Current, (Note 5)
Logic and Logic Reference Input
Current
Tj = 25˚C, Ch = 0.01 µF, VOUT = 0
Tj25˚C
Tj = 25˚C
0.5 2.0
4.5 5.5
2 10
1.0 2.5 mV
4.5 6.5 mA
2 10 µA
Leakage Current into Hold
Capacitor (Note 5)
Tj = 25˚C, (Note 7)
Hold Mode
30 100
30 200 pA
Acquisition Time to 0.1%
Hold Capacitor Charging Current
Supply Voltage Rejection Ratio
Differential Logic Threshold
Input Offset Voltage, (Note 5)
VOUT = 10V, Ch = 1000 pF
Ch = 0.01 µF
VIN−VOUT = 2V
VOUT = 0
Tj = 25˚C
Tj = 25˚C
Full Temperature Range
4
20
5
80 110
0.8 1.4
1
4
20
5
80 110
2.4 0.8 1.4 2.4
1 22
23
µs
µs
mA
dB
V
mV
mV
Input Bias Current, (Note 5)
Tj = 25˚C
Full Temperature Range
5 25
75
10 25 nA
50 nA
www.national.com
2


Part Number LF298
Description Monolithic Sample-and-Hold Circuits
Maker National Semiconductor
Total Page 13 Pages
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